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Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131578 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2011-05-18 21:25:14 +00:00
parent 673968ae78
commit 955db42568
1 changed files with 7 additions and 4 deletions
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11
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -1672,10 +1672,14 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
Ops.pop_back();
Ops.pop_back();
const TargetInstrDesc &TID = TII->get(NewOpc);
const TargetRegisterClass *TRC = TID.OpInfo[0].getRegClass(TRI);
MRI->constrainRegClass(EvenReg, TRC);
MRI->constrainRegClass(OddReg, TRC);
// Form the pair instruction.
if (isLd) {
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos,
dl, TII->get(NewOpc))
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TID)
.addReg(EvenReg, RegState::Define)
.addReg(OddReg, RegState::Define)
.addReg(BaseReg);
@ -1687,8 +1691,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
++NumLDRDFormed;
} else {
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos,
dl, TII->get(NewOpc))
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TID)
.addReg(EvenReg)
.addReg(OddReg)
.addReg(BaseReg);