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Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.

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SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
 their fields were totally screwed up. This seems to fix the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6429 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2003-05-30 08:02:14 +00:00
parent 261d686737
commit 9604416192
2 changed files with 7 additions and 3 deletions
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2
lib/Target/SparcV9/Makefile
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@ -36,7 +36,7 @@ SparcV9CodeEmitter.cpp: SparcV9CodeEmitter.inc
TEMP_EMITTER_INC = _temp_emitter.inc
SparcV9CodeEmitter.inc: SparcV9.td
SparcV9CodeEmitter.inc: SparcV9.td SparcV9_F2.td SparcV9_F3.td SparcV9_F4.td SparcV9_Reg.td
@echo "TableGen-erating $@"
cpp -P SparcV9.td | $(TBLGEN) -gen-emitter > $(TEMP_EMITTER_INC)
mv -f $(TEMP_EMITTER_INC) SparcV9CodeEmitter.inc

8
lib/Target/SparcV9/SparcV9_F3.td
View File

@ -108,9 +108,11 @@ class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
//set Inst{11-5} = dontcare;
}
class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3 {
class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1 {
bits<5> shcnt;
set op = opVal;
set op3 = op3Val;
set Name = name;
set Inst{13} = 1; // i field = 1
set Inst{12} = 0; // x field = 0
@ -118,9 +120,11 @@ class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3 {
set Inst{4-0} = shcnt;
}
class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3 {
class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1 {
bits<6> shcnt;
set op = opVal;
set op3 = op3Val;
set Name = name;
set Inst{13} = 1; // i field = 1
set Inst{12} = 1; // x field = 1