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R600/SI: fix MIMG writemask adjustement
This fixes piglit: - shaders/glsl-fs-texture2d-masked - shaders/glsl-fs-texture2d-masked-4 Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193222 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
f95b162188
commit
96b5670cf4
@ -1092,7 +1092,9 @@ static unsigned SubIdx2Lane(unsigned Idx) {
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void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
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SelectionDAG &DAG) const {
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SDNode *Users[4] = { };
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unsigned Writemask = 0, Lane = 0;
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unsigned Lane = 0;
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unsigned OldDmask = Node->getConstantOperandVal(0);
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unsigned NewDmask = 0;
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// Try to figure out the used register components
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for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
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@ -1103,29 +1105,42 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
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I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
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return;
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// Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
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// Note that subregs are packed, i.e. Lane==0 is the first bit set
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// in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
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// set, etc.
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Lane = SubIdx2Lane(I->getConstantOperandVal(1));
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// Set which texture component corresponds to the lane.
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unsigned Comp;
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for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
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assert(Dmask);
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Comp = ffs(Dmask)-1;
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Dmask &= ~(1 << Comp);
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}
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// Abort if we have more than one user per component
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if (Users[Lane])
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return;
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Users[Lane] = *I;
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Writemask |= 1 << Lane;
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NewDmask |= 1 << Comp;
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}
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// Abort if all components are used
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if (Writemask == 0xf)
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// Abort if there's no change
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if (NewDmask == OldDmask)
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return;
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// Adjust the writemask in the node
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std::vector<SDValue> Ops;
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Ops.push_back(DAG.getTargetConstant(Writemask, MVT::i32));
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Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
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for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
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Ops.push_back(Node->getOperand(i));
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Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
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// If we only got one lane, replace it with a copy
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if (Writemask == (1U << Lane)) {
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// (if NewDmask has only one bit set...)
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if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
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SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
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SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
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SDLoc(), Users[Lane]->getValueType(0),
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93
test/CodeGen/R600/llvm.SI.sample-masked.ll
Normal file
93
test/CodeGen/R600/llvm.SI.sample-masked.ll
Normal file
@ -0,0 +1,93 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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; CHECK-LABEL: @v1
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; CHECK: IMAGE_SAMPLE VGPR{{[[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}, 13
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define void @v1(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
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%2 = extractelement <4 x float> %1, i32 0
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%3 = extractelement <4 x float> %1, i32 2
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%4 = extractelement <4 x float> %1, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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ret void
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}
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; CHECK-LABEL: @v2
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; CHECK: IMAGE_SAMPLE VGPR{{[[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}, 11
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define void @v2(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
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%2 = extractelement <4 x float> %1, i32 0
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%3 = extractelement <4 x float> %1, i32 1
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%4 = extractelement <4 x float> %1, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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ret void
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}
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; CHECK-LABEL: @v3
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; CHECK: IMAGE_SAMPLE VGPR{{[[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}, 14
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define void @v3(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
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%2 = extractelement <4 x float> %1, i32 1
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%3 = extractelement <4 x float> %1, i32 2
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%4 = extractelement <4 x float> %1, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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ret void
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}
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; CHECK-LABEL: @v4
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; CHECK: IMAGE_SAMPLE VGPR{{[[0-9]}}_VGPR{{[0-9]}}_VGPR{{[0-9]}}, 7
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define void @v4(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
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%2 = extractelement <4 x float> %1, i32 0
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%3 = extractelement <4 x float> %1, i32 1
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%4 = extractelement <4 x float> %1, i32 2
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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ret void
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}
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; CHECK-LABEL: @v5
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; CHECK: IMAGE_SAMPLE VGPR{{[[0-9]}}_VGPR{{[0-9]}}, 10
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define void @v5(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
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%2 = extractelement <4 x float> %1, i32 1
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%3 = extractelement <4 x float> %1, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
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ret void
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}
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; CHECK-LABEL: @v6
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; CHECK: IMAGE_SAMPLE VGPR{{[[0-9]}}_VGPR{{[0-9]}}, 6
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define void @v6(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
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%2 = extractelement <4 x float> %1, i32 1
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%3 = extractelement <4 x float> %1, i32 2
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
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ret void
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}
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; CHECK-LABEL: @v7
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; CHECK: IMAGE_SAMPLE VGPR{{[[0-9]}}_VGPR{{[0-9]}}, 9
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define void @v7(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0)
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%2 = extractelement <4 x float> %1, i32 0
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%3 = extractelement <4 x float> %1, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
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ret void
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}
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declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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