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https://github.com/c64scene-ar/llvm-6502.git
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Refactor lock versions of binary operators to be a little less
cut and paste. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131139 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
f4351ceb93
commit
988397dcbc
@ -543,85 +543,95 @@ def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
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Requires<[In64BitMode]>, LOCK;
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// RegOpc corresponds to the mr version of the instruction
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// ImmOpc corresponds to the mi version of the instruction
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// ImmOpc8 corresponds to the mi8 version of the instruction
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// ImmMod corresponds to the instruction format of the mi and mi8 versions
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multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
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Format ImmMod, string mnemonic> {
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let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
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def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
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RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
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MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
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!strconcat("lock\n\t", mnemonic, "{b}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
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RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
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MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
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!strconcat("lock\n\t", mnemonic, "{w}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, OpSize, LOCK;
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def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
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RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
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MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
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!strconcat("lock\n\t", mnemonic, "{l}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
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RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
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MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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!strconcat("lock\n\t", mnemonic, "{q}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
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ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
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ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{b}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
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ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
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ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{w}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
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ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
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ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{l}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
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ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
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ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{q}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
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ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
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ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{w}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
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ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
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ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{l}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
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ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
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ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
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!strconcat("lock\n\t", mnemonic, "{q}\t",
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"{$src2, $dst|$dst, $src2}"),
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[]>, LOCK;
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}
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}
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defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
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defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
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// Optimized codegen when the non-memory output is not used.
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let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
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def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
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"lock\n\t"
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"add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
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"lock\n\t"
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"add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
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def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
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"lock\n\t"
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"add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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"lock\n\t"
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"add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
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"lock\n\t"
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"add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
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"lock\n\t"
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"add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
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"lock\n\t"
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"add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
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(ins i64mem:$dst, i64i32imm :$src2),
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"lock\n\t"
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"add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
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"lock\n\t"
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"add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
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def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
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"lock\n\t"
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"add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
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(ins i64mem:$dst, i64i8imm :$src2),
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"lock\n\t"
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"add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
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"lock\n\t"
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"sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
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"lock\n\t"
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"sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
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def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
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"lock\n\t"
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"sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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"lock\n\t"
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"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
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"lock\n\t"
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"sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
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"lock\n\t"
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"sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
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def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
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"lock\n\t"
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"sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
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(ins i64mem:$dst, i64i32imm:$src2),
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"lock\n\t"
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"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
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"lock\n\t"
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"sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
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def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
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"lock\n\t"
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"sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
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(ins i64mem:$dst, i64i8imm :$src2),
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"lock\n\t"
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"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
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def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
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"lock\n\t"
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