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R600: Non vector only instruction can be scheduled on trans unit

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune
2013-07-31 19:31:56 +00:00
parent a92f8ee2f3
commit 98ce62780e
29 changed files with 245 additions and 92 deletions
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2
test/CodeGen/R600/local-memory-two-objects.ll
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@ -12,7 +12,7 @@
; CHECK-NEXT: .long 8
; Make sure the lds writes are using different addresses.
; CHECK: LDS_WRITE {{[*]*}} {{PV|T}}[[ADDRW:[0-9]*\.[XYZW]]]
; CHECK: LDS_WRITE {{\** *}}{{PV|T}}[[ADDRW:[0-9]*\.[XYZW]]]
; CHECK-NOT: LDS_WRITE {{[*]*}} T[[ADDRW]]
; GROUP_BARRIER must be the last instruction in a clause