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https://github.com/c64scene-ar/llvm-6502.git
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- Two-address pass should not assume unfolding is always successful.
- X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107509 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
541481f34c
commit
98ec91ea80
@ -926,14 +926,12 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
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UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI);
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unsigned Reg = MRI->createVirtualRegister(RC);
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SmallVector<MachineInstr *, 2> NewMIs;
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bool Success =
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TII->unfoldMemoryOperand(MF, mi, Reg,
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/*UnfoldLoad=*/true, /*UnfoldStore=*/false,
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NewMIs);
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(void)Success;
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assert(Success &&
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"unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
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"succeeded!");
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if (!TII->unfoldMemoryOperand(MF, mi, Reg,
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/*UnfoldLoad=*/true,/*UnfoldStore=*/false,
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NewMIs)) {
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DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
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return false;
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}
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assert(NewMIs.size() == 2 &&
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"Unfolded a load into multiple instructions!");
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// The load was previously folded, so this is the only use.
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@ -2159,7 +2159,7 @@ void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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MachineInstr::mmo_iterator MMOBegin,
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MachineInstr::mmo_iterator MMOEnd,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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bool isAligned = (*MMOBegin)->getAlignment() >= 16;
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bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16;
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unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
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DebugLoc DL;
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
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@ -2189,7 +2189,7 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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MachineInstr::mmo_iterator MMOBegin,
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MachineInstr::mmo_iterator MMOEnd,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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bool isAligned = (*MMOBegin)->getAlignment() >= 16;
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bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16;
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unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
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DebugLoc DL;
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
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@ -2693,6 +2693,13 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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const TargetInstrDesc &TID = get(Opc);
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const TargetOperandInfo &TOI = TID.OpInfo[Index];
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const TargetRegisterClass *RC = TOI.getRegClass(&RI);
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if (!MI->hasOneMemOperand() &&
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RC == &X86::VR128RegClass &&
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!TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
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// Without memoperands, loadRegFromAddr and storeRegToStackSlot will
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// conservatively assume the address is unaligned. That's bad for
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// performance.
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return false;
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SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
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SmallVector<MachineOperand,2> BeforeOps;
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SmallVector<MachineOperand,2> AfterOps;
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@ -2834,7 +2841,12 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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MachineInstr::mmo_iterator> MMOs =
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MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
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cast<MachineSDNode>(N)->memoperands_end());
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bool isAligned = (*MMOs.first)->getAlignment() >= 16;
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if (!(*MMOs.first) &&
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RC == &X86::VR128RegClass &&
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!TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
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// Do not introduce a slow unaligned load.
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return false;
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bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
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Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
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VT, MVT::Other, &AddrOps[0], AddrOps.size());
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NewNodes.push_back(Load);
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@ -2871,7 +2883,12 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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MachineInstr::mmo_iterator> MMOs =
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MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
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cast<MachineSDNode>(N)->memoperands_end());
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bool isAligned = (*MMOs.first)->getAlignment() >= 16;
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if (!(*MMOs.first) &&
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RC == &X86::VR128RegClass &&
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!TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
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// Do not introduce a slow unaligned store.
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return false;
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bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
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SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
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isAligned, TM),
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dl, MVT::Other,
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99
test/CodeGen/X86/2010-07-02-UnfoldBug.ll
Normal file
99
test/CodeGen/X86/2010-07-02-UnfoldBug.ll
Normal file
@ -0,0 +1,99 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin
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; rdar://8154265
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declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone
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define void @_ZN2CA3OGL20fill_surface_mesh_3dERNS0_7ContextEPKNS_6Render13MeshTransformEPKNS0_5LayerEPNS0_7SurfaceEfNS0_13TextureFilterESC_f() nounwind optsize ssp {
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entry:
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br i1 undef, label %bb2.thread, label %bb2
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bb2.thread: ; preds = %entry
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br i1 undef, label %bb41, label %bb10.preheader
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bb2: ; preds = %entry
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unreachable
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bb10.preheader: ; preds = %bb2.thread
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br i1 undef, label %bb9, label %bb12
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bb9: ; preds = %bb9, %bb10.preheader
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br i1 undef, label %bb9, label %bb12
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bb12: ; preds = %bb9, %bb10.preheader
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br i1 undef, label %bb4.i.i, label %bb3.i.i
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bb3.i.i: ; preds = %bb12
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unreachable
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bb4.i.i: ; preds = %bb12
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br i1 undef, label %bb8.i.i, label %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit
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bb8.i.i: ; preds = %bb4.i.i
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br i1 undef, label %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit, label %bb9.i.i
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bb9.i.i: ; preds = %bb8.i.i
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br i1 undef, label %bb11.i.i, label %bb10.i.i
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bb10.i.i: ; preds = %bb9.i.i
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unreachable
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bb11.i.i: ; preds = %bb9.i.i
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unreachable
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_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit: ; preds = %bb8.i.i, %bb4.i.i
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br i1 undef, label %bb19, label %bb14
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bb14: ; preds = %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit
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unreachable
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bb19: ; preds = %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit
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br i1 undef, label %bb.i50, label %bb6.i
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bb.i50: ; preds = %bb19
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unreachable
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bb6.i: ; preds = %bb19
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br i1 undef, label %bb28, label %bb.nph106
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bb22: ; preds = %bb24.preheader
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br i1 undef, label %bb2.i.i, label %bb.i.i49
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bb.i.i49: ; preds = %bb22
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%0 = load float* undef, align 4 ; <float> [#uses=1]
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%1 = insertelement <4 x float> undef, float %0, i32 0 ; <<4 x float>> [#uses=1]
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%2 = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float 1.000000e+00, float undef, float undef, float undef>, <4 x float> %1) nounwind readnone ; <<4 x float>> [#uses=1]
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%3 = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %2, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>) nounwind readnone ; <<4 x float>> [#uses=1]
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%4 = extractelement <4 x float> %3, i32 0 ; <float> [#uses=1]
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store float %4, float* undef, align 4
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%5 = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float 1.000000e+00, float undef, float undef, float undef>, <4 x float> undef) nounwind readnone ; <<4 x float>> [#uses=1]
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%6 = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %5, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>) nounwind readnone ; <<4 x float>> [#uses=1]
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%7 = extractelement <4 x float> %6, i32 0 ; <float> [#uses=1]
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store float %7, float* undef, align 4
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unreachable
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bb2.i.i: ; preds = %bb22
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unreachable
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bb26.loopexit: ; preds = %bb24.preheader
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br i1 undef, label %bb28, label %bb24.preheader
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bb.nph106: ; preds = %bb6.i
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br label %bb24.preheader
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bb24.preheader: ; preds = %bb.nph106, %bb26.loopexit
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br i1 undef, label %bb22, label %bb26.loopexit
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bb28: ; preds = %bb26.loopexit, %bb6.i
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unreachable
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bb41: ; preds = %bb2.thread
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br i1 undef, label %return, label %bb46
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bb46: ; preds = %bb41
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ret void
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return: ; preds = %bb41
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ret void
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}
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