6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-18 12:29:27 +00:00
Code Issues Projects Releases Wiki Activity

remove extraneous &&'s from tests, as Scott is apparently not going to.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46173 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-01-18 19:53:43 +00:00
parent 9929207fde
commit 994d6cfb3d
20 changed files with 160 additions and 160 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
test/CodeGen/CellSPU/call.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep brsl %t1.s | count 1 &&
; RUN: grep brsl %t1.s | count 1
; RUN: grep brasl %t1.s | count 1
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"

26
test/CodeGen/CellSPU/call_indirect.ll
View File

@ -1,19 +1,19 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
; RUN: grep bisl %t1.s | count 7 &&
; RUN: grep ila %t1.s | count 1 &&
; RUN: grep rotqbyi %t1.s | count 4 &&
; RUN: grep lqa %t1.s | count 5 &&
; RUN: grep lqd %t1.s | count 6 &&
; RUN: grep bisl %t1.s | count 7
; RUN: grep ila %t1.s | count 1
; RUN: grep rotqbyi %t1.s | count 4
; RUN: grep lqa %t1.s | count 5
; RUN: grep lqd %t1.s | count 6
; RUN: grep dispatch_tab %t1.s | count 10
; RUN: grep bisl %t2.s | count 7 &&
; RUN: grep ilhu %t2.s | count 2 &&
; RUN: grep iohl %t2.s | count 2 &&
; RUN: grep rotqby %t2.s | count 6 &&
; RUN: grep lqd %t2.s | count 12 &&
; RUN: grep lqx %t2.s | count 8 &&
; RUN: grep il %t2.s | count 9 &&
; RUN: grep ai %t2.s | count 5 &&
; RUN: grep bisl %t2.s | count 7
; RUN: grep ilhu %t2.s | count 2
; RUN: grep iohl %t2.s | count 2
; RUN: grep rotqby %t2.s | count 6
; RUN: grep lqd %t2.s | count 12
; RUN: grep lqx %t2.s | count 8
; RUN: grep il %t2.s | count 9
; RUN: grep ai %t2.s | count 5
; RUN: grep dispatch_tab %t2.s | count 7
; ModuleID = 'call_indirect.bc'

6
test/CodeGen/CellSPU/ctpop.ll
View File

@ -1,7 +1,7 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep cntb %t1.s | count 3 &&
; RUN: grep andi %t1.s | count 3 &&
; RUN: grep rotmi %t1.s | count 2 &&
; RUN: grep cntb %t1.s | count 3
; RUN: grep andi %t1.s | count 3
; RUN: grep rotmi %t1.s | count 2
; RUN: grep rothmi %t1.s | count 1
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"

10
test/CodeGen/CellSPU/dp_farith.ll
View File

@ -1,9 +1,9 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep dfa %t1.s | count 2 &&
; RUN: grep dfs %t1.s | count 2 &&
; RUN: grep dfm %t1.s | count 6 &&
; RUN: grep dfma %t1.s | count 2 &&
; RUN: grep dfms %t1.s | count 2 &&
; RUN: grep dfa %t1.s | count 2
; RUN: grep dfs %t1.s | count 2
; RUN: grep dfm %t1.s | count 6
; RUN: grep dfma %t1.s | count 2
; RUN: grep dfms %t1.s | count 2
; RUN: grep dfnms %t1.s | count 4
;
; This file includes double precision floating point arithmetic instructions

6
test/CodeGen/CellSPU/eqv.ll
View File

@ -1,7 +1,7 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep eqv %t1.s | count 18 &&
; RUN: grep xshw %t1.s | count 6 &&
; RUN: grep xsbh %t1.s | count 3 &&
; RUN: grep eqv %t1.s | count 18
; RUN: grep xshw %t1.s | count 6
; RUN: grep xsbh %t1.s | count 3
; RUN: grep andi %t1.s | count 3
; Test the 'eqv' instruction, whose boolean expression is:

8
test/CodeGen/CellSPU/extract_elt.ll
View File

@ -1,9 +1,9 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
; RUN: grep shufb %t1.s | count 27 &&
; RUN: grep lqa %t1.s | count 27 &&
; RUN: grep lqx %t2.s | count 27 &&
; RUN: grep space %t1.s | count 8 &&
; RUN: grep shufb %t1.s | count 27
; RUN: grep lqa %t1.s | count 27
; RUN: grep lqx %t2.s | count 27
; RUN: grep space %t1.s | count 8
; RUN: grep byte %t1.s | count 424
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"

8
test/CodeGen/CellSPU/fdiv.ll
View File

@ -1,8 +1,8 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep frest %t1.s | count 2 &&
; RUN: grep fi %t1.s | count 2 &&
; RUN: grep fm %t1.s | count 4 &&
; RUN: grep fma %t1.s | count 2 &&
; RUN: grep frest %t1.s | count 2
; RUN: grep fi %t1.s | count 2
; RUN: grep fm %t1.s | count 4
; RUN: grep fma %t1.s | count 2
; RUN: grep fnms %t1.s | count 2
;
; This file includes standard floating point arithmetic instructions

8
test/CodeGen/CellSPU/fneg-fabs.ll
View File

@ -1,8 +1,8 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep fsmbi %t1.s | count 3 &&
; RUN: grep 32768 %t1.s | count 2 &&
; RUN: grep xor %t1.s | count 4 &&
; RUN: grep and %t1.s | count 5 &&
; RUN: grep fsmbi %t1.s | count 3
; RUN: grep 32768 %t1.s | count 2
; RUN: grep xor %t1.s | count 4
; RUN: grep and %t1.s | count 5
; RUN: grep andbi %t1.s | count 3
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"

24
test/CodeGen/CellSPU/immed32.ll
View File

@ -1,16 +1,16 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep ilhu %t1.s | count 8 &&
; RUN: grep iohl %t1.s | count 6 &&
; RUN: grep il %t1.s | count 11 &&
; RUN: grep 16429 %t1.s | count 1 &&
; RUN: grep 63572 %t1.s | count 1 &&
; RUN: grep 128 %t1.s | count 1 &&
; RUN: grep 32639 %t1.s | count 1 &&
; RUN: grep 65535 %t1.s | count 1 &&
; RUN: grep 16457 %t1.s | count 1 &&
; RUN: grep 4059 %t1.s | count 1 &&
; RUN: grep 49077 %t1.s | count 1 &&
; RUN: grep 1267 %t1.s | count 2 &&
; RUN: grep ilhu %t1.s | count 8
; RUN: grep iohl %t1.s | count 6
; RUN: grep il %t1.s | count 11
; RUN: grep 16429 %t1.s | count 1
; RUN: grep 63572 %t1.s | count 1
; RUN: grep 128 %t1.s | count 1
; RUN: grep 32639 %t1.s | count 1
; RUN: grep 65535 %t1.s | count 1
; RUN: grep 16457 %t1.s | count 1
; RUN: grep 4059 %t1.s | count 1
; RUN: grep 49077 %t1.s | count 1
; RUN: grep 1267 %t1.s | count 2
; RUN: grep 16309 %t1.s | count 1
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"

20
test/CodeGen/CellSPU/immed64.ll
View File

@ -1,14 +1,14 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep lqa %t1.s | count 13 &&
; RUN: grep shufb %t1.s | count 13 &&
; RUN: grep 65520 %t1.s | count 1 &&
; RUN: grep 43981 %t1.s | count 1 &&
; RUN: grep 13702 %t1.s | count 1 &&
; RUN: grep 81 %t1.s | count 2 &&
; RUN: grep 28225 %t1.s | count 1 &&
; RUN: grep 30720 %t1.s | count 1 &&
; RUN: grep 192 %t1.s | count 32 &&
; RUN: grep 128 %t1.s | count 30 &&
; RUN: grep lqa %t1.s | count 13
; RUN: grep shufb %t1.s | count 13
; RUN: grep 65520 %t1.s | count 1
; RUN: grep 43981 %t1.s | count 1
; RUN: grep 13702 %t1.s | count 1
; RUN: grep 81 %t1.s | count 2
; RUN: grep 28225 %t1.s | count 1
; RUN: grep 30720 %t1.s | count 1
; RUN: grep 192 %t1.s | count 32
; RUN: grep 128 %t1.s | count 30
; RUN: grep 224 %t1.s | count 2
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"

12
test/CodeGen/CellSPU/int2fp.ll
View File

@ -1,10 +1,10 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep csflt %t1.s | count 5 &&
; RUN: grep cuflt %t1.s | count 1 &&
; RUN: grep xshw %t1.s | count 2 &&
; RUN: grep xsbh %t1.s | count 1 &&
; RUN: grep and %t1.s | count 2 &&
; RUN: grep andi %t1.s | count 1 &&
; RUN: grep csflt %t1.s | count 5
; RUN: grep cuflt %t1.s | count 1
; RUN: grep xshw %t1.s | count 2
; RUN: grep xsbh %t1.s | count 1
; RUN: grep and %t1.s | count 2
; RUN: grep andi %t1.s | count 1
; RUN: grep ila %t1.s | count 1
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"

14
test/CodeGen/CellSPU/intrinsics_branch.ll
View File

@ -1,11 +1,11 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep ceq %t1.s | count 30 &&
; RUN: grep ceqb %t1.s | count 10 &&
; RUN: grep ceqhi %t1.s | count 5 &&
; RUN: grep ceqi %t1.s | count 5 &&
; RUN: grep cgt %t1.s | count 30 &&
; RUN: grep cgtb %t1.s | count 10 &&
; RUN: grep cgthi %t1.s | count 5 &&
; RUN: grep ceq %t1.s | count 30
; RUN: grep ceqb %t1.s | count 10
; RUN: grep ceqhi %t1.s | count 5
; RUN: grep ceqi %t1.s | count 5
; RUN: grep cgt %t1.s | count 30
; RUN: grep cgtb %t1.s | count 10
; RUN: grep cgthi %t1.s | count 5
; RUN: grep cgti %t1.s | count 5
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"

20
test/CodeGen/CellSPU/intrinsics_float.ll
View File

@ -1,13 +1,13 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep fa %t1.s | count 5 &&
; RUN: grep fs %t1.s | count 5 &&
; RUN: grep fm %t1.s | count 15 &&
; RUN: grep fceq %t1.s | count 5 &&
; RUN: grep fcmeq %t1.s | count 5 &&
; RUN: grep fcgt %t1.s | count 5 &&
; RUN: grep fcmgt %t1.s | count 5 &&
; RUN: grep fma %t1.s | count 5 &&
; RUN: grep fnms %t1.s | count 5 &&
; RUN: grep fa %t1.s | count 5
; RUN: grep fs %t1.s | count 5
; RUN: grep fm %t1.s | count 15
; RUN: grep fceq %t1.s | count 5
; RUN: grep fcmeq %t1.s | count 5
; RUN: grep fcgt %t1.s | count 5
; RUN: grep fcmgt %t1.s | count 5
; RUN: grep fma %t1.s | count 5
; RUN: grep fnms %t1.s | count 5
; RUN: grep fms %t1.s | count 5
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"
@ -91,4 +91,4 @@ define <4 x float> @fmstest(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
call <4 x float> @llvm.spu.si.fms(<4 x float> %A, <4 x float> %B, <4 x float> %C)
%Y = bitcast <4 x float> %1 to <4 x float>
ret <4 x float> %Y
}
}

2
test/CodeGen/CellSPU/intrinsics_logical.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep and %t1.s | count 20 &&
; RUN: grep and %t1.s | count 20
; RUN: grep andc %t1.s | count 5
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"

26
test/CodeGen/CellSPU/mul_ops.ll
View File

@ -1,17 +1,17 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep mpy %t1.s | count 44 &&
; RUN: grep mpyu %t1.s | count 4 &&
; RUN: grep mpyh %t1.s | count 10 &&
; RUN: grep mpyhh %t1.s | count 2 &&
; RUN: grep rotma %t1.s | count 12 &&
; RUN: grep rotmahi %t1.s | count 4 &&
; RUN: grep and %t1.s | count 2 &&
; RUN: grep selb %t1.s | count 6 &&
; RUN: grep fsmbi %t1.s | count 4 &&
; RUN: grep shli %t1.s | count 4 &&
; RUN: grep shlhi %t1.s | count 4 &&
; RUN: grep ila %t1.s | count 2 &&
; RUN: grep xsbh %t1.s | count 8 &&
; RUN: grep mpy %t1.s | count 44
; RUN: grep mpyu %t1.s | count 4
; RUN: grep mpyh %t1.s | count 10
; RUN: grep mpyhh %t1.s | count 2
; RUN: grep rotma %t1.s | count 12
; RUN: grep rotmahi %t1.s | count 4
; RUN: grep and %t1.s | count 2
; RUN: grep selb %t1.s | count 6
; RUN: grep fsmbi %t1.s | count 4
; RUN: grep shli %t1.s | count 4
; RUN: grep shlhi %t1.s | count 4
; RUN: grep ila %t1.s | count 2
; RUN: grep xsbh %t1.s | count 8
; RUN: grep xshw %t1.s | count 4
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"

10
test/CodeGen/CellSPU/sp_farith.ll
View File

@ -1,9 +1,9 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep fa %t1.s | count 2 &&
; RUN: grep fs %t1.s | count 2 &&
; RUN: grep fm %t1.s | count 6 &&
; RUN: grep fma %t1.s | count 2 &&
; RUN: grep fms %t1.s | count 2 &&
; RUN: grep fa %t1.s | count 2
; RUN: grep fs %t1.s | count 2
; RUN: grep fm %t1.s | count 6
; RUN: grep fma %t1.s | count 2
; RUN: grep fms %t1.s | count 2
; RUN: grep fnms %t1.s | count 3
;
; This file includes standard floating point arithmetic instructions

40
test/CodeGen/CellSPU/struct_1.ll
View File

@ -1,26 +1,26 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
; RUN: grep lqa %t1.s | count 10 &&
; RUN: grep lqd %t1.s | count 4 &&
; RUN: grep rotqbyi %t1.s | count 5 &&
; RUN: grep xshw %t1.s | count 1 &&
; RUN: grep andi %t1.s | count 4 &&
; RUN: grep cbd %t1.s | count 3 &&
; RUN: grep chd %t1.s | count 1 &&
; RUN: grep cwd %t1.s | count 3 &&
; RUN: grep shufb %t1.s | count 7 &&
; RUN: grep lqa %t1.s | count 10
; RUN: grep lqd %t1.s | count 4
; RUN: grep rotqbyi %t1.s | count 5
; RUN: grep xshw %t1.s | count 1
; RUN: grep andi %t1.s | count 4
; RUN: grep cbd %t1.s | count 3
; RUN: grep chd %t1.s | count 1
; RUN: grep cwd %t1.s | count 3
; RUN: grep shufb %t1.s | count 7
; RUN: grep stqa %t1.s | count 5
; RUN: grep iohl %t2.s | count 14 &&
; RUN: grep ilhu %t2.s | count 14 &&
; RUN: grep lqx %t2.s | count 14 &&
; RUN: grep rotqbyi %t2.s | count 5 &&
; RUN: grep xshw %t2.s | count 1 &&
; RUN: grep andi %t2.s | count 4 &&
; RUN: grep cbx %t2.s | count 3 &&
; RUN: grep chx %t2.s | count 1 &&
; RUN: grep cwx %t2.s | count 1 &&
; RUN: grep cwd %t2.s | count 2 &&
; RUN: grep shufb %t2.s | count 7 &&
; RUN: grep iohl %t2.s | count 14
; RUN: grep ilhu %t2.s | count 14
; RUN: grep lqx %t2.s | count 14
; RUN: grep rotqbyi %t2.s | count 5
; RUN: grep xshw %t2.s | count 1
; RUN: grep andi %t2.s | count 4
; RUN: grep cbx %t2.s | count 3
; RUN: grep chx %t2.s | count 1
; RUN: grep cwx %t2.s | count 1
; RUN: grep cwd %t2.s | count 2
; RUN: grep shufb %t2.s | count 7
; RUN: grep stqx %t2.s | count 7
; ModuleID = 'struct_1.bc'

18
test/CodeGen/CellSPU/struct_2.ll
View File

@ -1,13 +1,13 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep lqx %t1.s | count 14 &&
; RUN: grep rotqby %t1.s | count 7 &&
; RUN: grep xshw %t1.s | count 1 &&
; RUN: grep andi %t1.s | count 4 &&
; RUN: grep cbx %t1.s | count 1 &&
; RUN: grep cbd %t1.s | count 2 &&
; RUN: grep chd %t1.s | count 1 &&
; RUN: grep cwd %t1.s | count 3 &&
; RUN: grep shufb %t1.s | count 7 &&
; RUN: grep lqx %t1.s | count 14
; RUN: grep rotqby %t1.s | count 7
; RUN: grep xshw %t1.s | count 1
; RUN: grep andi %t1.s | count 4
; RUN: grep cbx %t1.s | count 1
; RUN: grep cbd %t1.s | count 2
; RUN: grep chd %t1.s | count 1
; RUN: grep cwd %t1.s | count 3
; RUN: grep shufb %t1.s | count 7
; RUN: grep stqx %t1.s | count 7
; ModuleID = 'struct_1.bc'

36
test/CodeGen/CellSPU/vec_const.ll
View File

@ -1,23 +1,23 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
; RUN: grep il %t1.s | count 16 &&
; RUN: grep ilhu %t1.s | count 8 &&
; RUN: grep ilh %t1.s | count 13 &&
; RUN: grep iohl %t1.s | count 7 &&
; RUN: grep lqa %t1.s | count 6 &&
; RUN: grep 24672 %t1.s | count 2 &&
; RUN: grep 16429 %t1.s | count 1 &&
; RUN: grep 63572 %t1.s | count 1 &&
; RUN: grep 4660 %t1.s | count 1 &&
; RUN: grep 22136 %t1.s | count 1 &&
; RUN: grep 43981 %t1.s | count 1 &&
; RUN: grep 61202 %t1.s | count 1 &&
; RUN: grep 16393 %t1.s | count 1 &&
; RUN: grep 8699 %t1.s | count 1 &&
; RUN: grep 21572 %t1.s | count 1 &&
; RUN: grep 11544 %t1.s | count 1 &&
; RUN: grep 1311768467750121234 %t1.s | count 1 &&
; RUN: grep lqx %t2.s | count 6 &&
; RUN: grep il %t1.s | count 16
; RUN: grep ilhu %t1.s | count 8
; RUN: grep ilh %t1.s | count 13
; RUN: grep iohl %t1.s | count 7
; RUN: grep lqa %t1.s | count 6
; RUN: grep 24672 %t1.s | count 2
; RUN: grep 16429 %t1.s | count 1
; RUN: grep 63572 %t1.s | count 1
; RUN: grep 4660 %t1.s | count 1
; RUN: grep 22136 %t1.s | count 1
; RUN: grep 43981 %t1.s | count 1
; RUN: grep 61202 %t1.s | count 1
; RUN: grep 16393 %t1.s | count 1
; RUN: grep 8699 %t1.s | count 1
; RUN: grep 21572 %t1.s | count 1
; RUN: grep 11544 %t1.s | count 1
; RUN: grep 1311768467750121234 %t1.s | count 1
; RUN: grep lqx %t2.s | count 6
; RUN: grep ila %t2.s | count 6
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"

24
test/CodeGen/CellSPU/vecinsert.ll
View File

@ -1,16 +1,16 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep cbd %t1.s | count 3 &&
; RUN: grep chd %t1.s | count 3 &&
; RUN: grep cwd %t1.s | count 6 &&
; RUN: grep il %t1.s | count 4 &&
; RUN: grep ilh %t1.s | count 3 &&
; RUN: grep iohl %t1.s | count 1 &&
; RUN: grep ilhu %t1.s | count 1 &&
; RUN: grep shufb %t1.s | count 12 &&
; RUN: grep 17219 %t1.s | count 1 &&
; RUN: grep 22598 %t1.s | count 1 &&
; RUN: grep -- -39 %t1.s | count 1 &&
; RUN: grep 24 %t1.s | count 1 &&
; RUN: grep cbd %t1.s | count 3
; RUN: grep chd %t1.s | count 3
; RUN: grep cwd %t1.s | count 6
; RUN: grep il %t1.s | count 4
; RUN: grep ilh %t1.s | count 3
; RUN: grep iohl %t1.s | count 1
; RUN: grep ilhu %t1.s | count 1
; RUN: grep shufb %t1.s | count 12
; RUN: grep 17219 %t1.s | count 1
; RUN: grep 22598 %t1.s | count 1
; RUN: grep -- -39 %t1.s | count 1
; RUN: grep 24 %t1.s | count 1
; RUN: grep 1159 %t1.s | count 1
; ModuleID = 'vecinsert.bc'
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"