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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-27 14:34:58 +00:00
implement missing compares
patch by Lauro bug fixed by me git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32795 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
parent
1fd79b8c42
commit
9985f9f61e
@ -151,59 +151,62 @@ namespace llvm {
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/// DAGFPCCToARMCC - Convert a DAG fp condition code to an ARM CC
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// Unordered = !N & !Z & C & V = V
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// Ordered = N | Z | !C | !V = N | Z | !V
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static ARMCC::CondCodes DAGFPCCToARMCC(ISD::CondCode CC) {
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static std::vector<unsigned> DAGFPCCToARMCC(ISD::CondCode CC) {
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switch (CC) {
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default:
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assert(0 && "Unknown fp condition code!");
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// SETOEQ = (N | Z | !V) & Z = Z = EQ
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case ISD::SETEQ:
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case ISD::SETOEQ: return ARMCC::EQ;
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case ISD::SETOEQ: return make_vector<unsigned>(ARMCC::EQ, 0);
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// SETOGT = (N | Z | !V) & !N & !Z = !V &!N &!Z = (N = V) & !Z = GT
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case ISD::SETGT:
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case ISD::SETOGT: return ARMCC::GT;
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case ISD::SETOGT: return make_vector<unsigned>(ARMCC::GT, 0);
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// SETOGE = (N | Z | !V) & !N = (Z | !V) & !N = !V & !N = GE
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case ISD::SETGE:
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case ISD::SETOGE: return ARMCC::GE;
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case ISD::SETOGE: return make_vector<unsigned>(ARMCC::GE, 0);
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// SETOLT = (N | Z | !V) & N = N = MI
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case ISD::SETLT:
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case ISD::SETOLT: return ARMCC::MI;
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case ISD::SETOLT: return make_vector<unsigned>(ARMCC::MI, 0);
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// SETOLE = (N | Z | !V) & (N | Z) = N | Z = !C | Z = LS
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case ISD::SETLE:
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case ISD::SETOLE: return ARMCC::LS;
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// SETONE = (N | Z | !V) & !Z = (N | !V) & !Z = !V & !Z = !Z = NE
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case ISD::SETNE:
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case ISD::SETONE: return ARMCC::NE;
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case ISD::SETOLE: return make_vector<unsigned>(ARMCC::LS, 0);
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// SETONE = OGT | OLT
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case ISD::SETONE: return make_vector<unsigned>(ARMCC::GT, ARMCC::MI, 0);
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// SETO = N | Z | !V = Z | !V = !V = VC
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case ISD::SETO: return ARMCC::VC;
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case ISD::SETO: return make_vector<unsigned>(ARMCC::VC, 0);
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// SETUO = V = VS
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case ISD::SETUO: return ARMCC::VS;
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// SETUEQ = V | Z = ??
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case ISD::SETUO: return make_vector<unsigned>(ARMCC::VS, 0);
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// SETUEQ = V | Z (need two instructions) = EQ/VS
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case ISD::SETUEQ: return make_vector<unsigned>(ARMCC::EQ, ARMCC::VS, 0);
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// SETUGT = V | (!Z & !N) = !Z & !N = !Z & C = HI
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case ISD::SETUGT: return ARMCC::HI;
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case ISD::SETUGT: return make_vector<unsigned>(ARMCC::HI, 0);
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// SETUGE = V | !N = !N = PL
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case ISD::SETUGE: return ARMCC::PL;
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// SETULT = V | N = ??
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// SETULE = V | Z | N = ??
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case ISD::SETUGE: return make_vector<unsigned>(ARMCC::PL, 0);
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// SETULT = V | N = LT
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case ISD::SETULT: return make_vector<unsigned>(ARMCC::LT, 0);
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// SETULE = V | Z | N = LE
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case ISD::SETULE: return make_vector<unsigned>(ARMCC::LE, 0);
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// SETUNE = V | !Z = !Z = NE
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case ISD::SETUNE: return ARMCC::NE;
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case ISD::SETNE:
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case ISD::SETUNE: return make_vector<unsigned>(ARMCC::NE, 0);
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}
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}
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/// DAGIntCCToARMCC - Convert a DAG integer condition code to an ARM CC
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static ARMCC::CondCodes DAGIntCCToARMCC(ISD::CondCode CC) {
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static std::vector<unsigned> DAGIntCCToARMCC(ISD::CondCode CC) {
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switch (CC) {
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default:
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assert(0 && "Unknown integer condition code!");
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case ISD::SETEQ: return ARMCC::EQ;
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case ISD::SETNE: return ARMCC::NE;
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case ISD::SETLT: return ARMCC::LT;
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case ISD::SETLE: return ARMCC::LE;
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case ISD::SETGT: return ARMCC::GT;
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case ISD::SETGE: return ARMCC::GE;
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case ISD::SETULT: return ARMCC::CC;
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case ISD::SETULE: return ARMCC::LS;
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case ISD::SETUGT: return ARMCC::HI;
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case ISD::SETUGE: return ARMCC::CS;
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case ISD::SETEQ: return make_vector<unsigned>(ARMCC::EQ, 0);
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case ISD::SETNE: return make_vector<unsigned>(ARMCC::NE, 0);
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case ISD::SETLT: return make_vector<unsigned>(ARMCC::LT, 0);
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case ISD::SETLE: return make_vector<unsigned>(ARMCC::LE, 0);
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case ISD::SETGT: return make_vector<unsigned>(ARMCC::GT, 0);
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case ISD::SETGE: return make_vector<unsigned>(ARMCC::GE, 0);
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case ISD::SETULT: return make_vector<unsigned>(ARMCC::CC, 0);
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case ISD::SETULE: return make_vector<unsigned>(ARMCC::LS, 0);
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case ISD::SETUGT: return make_vector<unsigned>(ARMCC::HI, 0);
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case ISD::SETUGE: return make_vector<unsigned>(ARMCC::CS, 0);
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}
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}
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@ -653,13 +656,20 @@ static SDOperand GetCMP(ISD::CondCode CC, SDOperand LHS, SDOperand RHS,
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return Cmp;
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}
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static SDOperand GetARMCC(ISD::CondCode CC, MVT::ValueType vt,
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static std::vector<SDOperand> GetARMCC(ISD::CondCode CC, MVT::ValueType vt,
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SelectionDAG &DAG) {
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assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64);
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std::vector<unsigned> vcc;
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if (vt == MVT::i32)
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return DAG.getConstant(DAGIntCCToARMCC(CC), MVT::i32);
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vcc = DAGIntCCToARMCC(CC);
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else
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return DAG.getConstant(DAGFPCCToARMCC(CC), MVT::i32);
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vcc = DAGFPCCToARMCC(CC);
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std::vector<unsigned>::iterator it;
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std::vector<SDOperand> result;
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for( it = vcc.begin(); it != vcc.end(); it++ )
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result.push_back(DAG.getConstant(*it,MVT::i32));
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return result;
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}
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static bool isUInt8Immediate(uint32_t x) {
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@ -682,8 +692,9 @@ static bool isRotInt8Immediate(uint32_t x) {
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return false;
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}
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static void LowerCMP(SDOperand &Cmp, SDOperand &ARMCC, SDOperand LHS,
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SDOperand RHS, ISD::CondCode CC, SelectionDAG &DAG) {
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static void LowerCMP(SDOperand &Cmp, std::vector<SDOperand> &ARMCC,
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SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
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SelectionDAG &DAG) {
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MVT::ValueType vt = LHS.getValueType();
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if (vt == MVT::i32) {
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assert(!isa<ConstantSDNode>(LHS));
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@ -745,9 +756,18 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand TrueVal = Op.getOperand(2);
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SDOperand FalseVal = Op.getOperand(3);
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SDOperand Cmp;
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SDOperand ARMCC;
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std::vector<SDOperand> ARMCC;
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LowerCMP(Cmp, ARMCC, LHS, RHS, CC, DAG);
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return DAG.getNode(ARMISD::SELECT, Op.getValueType(), TrueVal, FalseVal, ARMCC, Cmp);
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SDOperand Aux = FalseVal;
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SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
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std::vector<SDOperand>::iterator it;
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for (it = ARMCC.begin(); it != ARMCC.end(); ++it){
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SDOperand Flag = it == ARMCC.begin() ? Cmp : Aux.getValue(1);
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SDOperand Ops[] = {TrueVal, Aux, *it, Flag};
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Aux = DAG.getNode(ARMISD::SELECT, VTs, Ops, 4);
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}
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return Aux;
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}
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static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
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@ -757,9 +777,18 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand RHS = Op.getOperand(3);
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SDOperand Dest = Op.getOperand(4);
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SDOperand Cmp;
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SDOperand ARMCC;
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std::vector<SDOperand> ARMCC;
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LowerCMP(Cmp, ARMCC, LHS, RHS, CC, DAG);
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return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
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SDOperand Aux = Chain;
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SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
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std::vector<SDOperand>::iterator it;
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for (it = ARMCC.begin(); it != ARMCC.end(); it++){
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SDOperand Flag = it == ARMCC.begin() ? Cmp : Aux.getValue(1);
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SDOperand Ops[] = {Aux, Dest, *it, Flag};
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Aux = DAG.getNode(ARMISD::BR, VTs, Ops, 4);
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}
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return Aux;
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}
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static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
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@ -109,7 +109,7 @@ def SDTarmfmstat : SDTypeProfile<0, 0, []>;
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def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
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def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
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def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
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def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
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11
test/CodeGen/ARM/fpcmp_ueq.ll
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11
test/CodeGen/ARM/fpcmp_ueq.ll
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@ -0,0 +1,11 @@
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; RUN: llvm-as < %s | llc -march=arm &&
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; RUN: llvm-as < %s | llc -march=arm | grep moveq &&
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; RUN: llvm-as < %s | llc -march=arm | grep movvs
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define i32 %f7(float %a, float %b) {
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entry:
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%tmp = fcmp ueq float %a,%b
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%retval = select bool %tmp, i32 666, i32 42
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ret i32 %retval
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}
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