6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 04:56:49 +00:00
Code Issues Projects Releases Wiki Activity

Remove some special-case logic in ScheduleDAGSDNodes's

Browse Source 
latency computation code that is no longer needed with the
new method for handling latencies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61074 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-12-16 03:31:11 +00:00
parent 3f23744df4
commit 9a65d6afc2
1 changed files with 0 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
View File

@ -196,12 +196,6 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
// Compute the latency for the node. We use the sum of the latencies for
// all nodes flagged together into this SUnit.
if (InstrItins.isEmpty()) {
// No latency information.
SU->Latency = 1;
return;
}
SU->Latency = 0;
bool SawMachineOpcode = false;
for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
@ -210,10 +204,6 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
SU->Latency +=
InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
}
// Ensure that CopyToReg and similar nodes have a non-zero latency.
if (!SawMachineOpcode)
SU->Latency = 1;
}
/// CountResults - The results of target nodes have register or immediate