6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

Noone calls these virtual methods

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11982 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-02-29 05:58:16 +00:00
parent 0723969e87
commit 9a945277c0
1 changed files with 0 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
lib/Target/SparcV9/SparcV9InstrInfo.h
View File

@ -48,32 +48,6 @@ struct SparcV9InstrInfo : public TargetInstrInfo {
return -1;
}
/// createNOPinstr - returns the target's implementation of NOP, which is
/// usually a pseudo-instruction, implemented by a degenerate version of
/// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
///
MachineInstr* createNOPinstr() const {
return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcV9IntRegClass::g0);
}
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
/// more than one way to `do nothing' but only one canonical way to slack off.
///
bool isNOPinstr(const MachineInstr &MI) const {
// Make sure the instruction is EXACTLY `sethi g0, 0'
if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
if (op0.isImmediate() && op0.getImmedValue() == 0 &&
op1.getType() == MachineOperand::MO_MachineRegister &&
op1.getMachineRegNum() == SparcV9IntRegClass::g0)
{
return true;
}
}
return false;
}
virtual bool hasResultInterlock(MachineOpCode opCode) const
{
// All UltraSPARC instructions have interlocks (note that delay slots