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zext / truncate is free on msp430. Inform codegen about this.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93556 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2010-01-15 21:19:43 +00:00
parent 12c71a53b5
commit 9afb7c5fb3
2 changed files with 42 additions and 0 deletions
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25
lib/Target/MSP430/MSP430ISelLowering.cpp
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@ -967,6 +967,31 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
bool MSP430TargetLowering::isTruncateFree(const Type *Ty1,
const Type *Ty2) const {
if (!Ty1->isInteger() || !Ty2->isInteger())
return false;
return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
}
bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
if (!VT1.isInteger() || !VT2.isInteger())
return false;
return (VT1.getSizeInBits() > VT2.getSizeInBits());
}
bool MSP430TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
// MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
return 0 && Ty1->isInteger(8) && Ty2->isInteger(16);
}
bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
// MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
}
//===----------------------------------------------------------------------===//
// Other Lowering Code
//===----------------------------------------------------------------------===//

17
lib/Target/MSP430/MSP430ISelLowering.h
View File

@ -99,6 +99,23 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
/// isTruncateFree - Return true if it's free to truncate a value of type
/// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
/// register R15W to i8 by referencing its sub-register R15B.
virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
/// isZExtFree - Return true if any actual instruction that defines a value
/// of type Ty1 implicit zero-extends the value to Ty2 in the result
/// register. This does not necessarily include registers defined in unknown
/// ways, such as incoming arguments, or copies from unknown virtual
/// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
/// necessarily apply to truncate instructions. e.g. on msp430, all
/// instructions that define 8-bit values implicit zero-extend the result
/// out to 16 bits.
virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
virtual bool isZExtFree(EVT VT1, EVT VT2) const;
MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB,
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;