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x86 -- add the XTEST instruction

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dave Zarzycki 2013-03-25 18:59:43 +00:00
parent 97a80092d3
commit 9b3939983f
6 changed files with 43 additions and 39 deletions
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23
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
View File

@ -276,9 +276,9 @@ namespace X86II {
MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, MRM_C4 = 36,
MRM_C8 = 37, MRM_C9 = 38, MRM_E8 = 39, MRM_F0 = 40,
MRM_F8 = 41, MRM_F9 = 42, MRM_D0 = 45, MRM_D1 = 46,
MRM_D4 = 47, MRM_D5 = 48, MRM_D8 = 49, MRM_D9 = 50,
MRM_DA = 51, MRM_DB = 52, MRM_DC = 53, MRM_DD = 54,
MRM_DE = 55, MRM_DF = 56,
MRM_D4 = 47, MRM_D5 = 48, MRM_D6 = 49, MRM_D8 = 50,
MRM_D9 = 51, MRM_DA = 52, MRM_DB = 53, MRM_DC = 54,
MRM_DD = 55, MRM_DE = 56, MRM_DF = 57,
/// RawFrmImm8 - This is used for the ENTER instruction, which has two
/// immediates, the first of which is a 16-bit immediate (specified by
@ -574,16 +574,13 @@ namespace X86II {
++FirstMemOp;// Skip the register dest (which is encoded in VEX_VVVV).
return FirstMemOp;
}
case X86II::MRM_C1: case X86II::MRM_C2:
case X86II::MRM_C3: case X86II::MRM_C4:
case X86II::MRM_C8: case X86II::MRM_C9:
case X86II::MRM_E8: case X86II::MRM_F0:
case X86II::MRM_F8: case X86II::MRM_F9:
case X86II::MRM_D0: case X86II::MRM_D1:
case X86II::MRM_D4: case X86II::MRM_D5:
case X86II::MRM_D8: case X86II::MRM_D9:
case X86II::MRM_DA: case X86II::MRM_DB:
case X86II::MRM_DC: case X86II::MRM_DD:
case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
case X86II::MRM_F9: case X86II::MRM_D0: case X86II::MRM_D1:
case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
case X86II::MRM_DE: case X86II::MRM_DF:
return -1;
}

18
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -1136,16 +1136,13 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
TSFlags, CurByte, OS, Fixups);
CurOp += X86::AddrNumOperands;
break;
case X86II::MRM_C1: case X86II::MRM_C2:
case X86II::MRM_C3: case X86II::MRM_C4:
case X86II::MRM_C8: case X86II::MRM_C9:
case X86II::MRM_D0: case X86II::MRM_D1:
case X86II::MRM_D4: case X86II::MRM_D5:
case X86II::MRM_D8: case X86II::MRM_D9:
case X86II::MRM_DA: case X86II::MRM_DB:
case X86II::MRM_DC: case X86II::MRM_DD:
case X86II::MRM_DE: case X86II::MRM_DF:
case X86II::MRM_E8: case X86II::MRM_F0:
case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
case X86II::MRM_DF: case X86II::MRM_E8: case X86II::MRM_F0:
case X86II::MRM_F8: case X86II::MRM_F9:
EmitByte(BaseOpcode, CurByte, OS);
@ -1162,6 +1159,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
case X86II::MRM_D1: MRM = 0xD1; break;
case X86II::MRM_D4: MRM = 0xD4; break;
case X86II::MRM_D5: MRM = 0xD5; break;
case X86II::MRM_D6: MRM = 0xD6; break;
case X86II::MRM_D8: MRM = 0xD8; break;
case X86II::MRM_D9: MRM = 0xD9; break;
case X86II::MRM_DA: MRM = 0xDA; break;

17
lib/Target/X86/X86InstrFormats.td
View File

@ -45,14 +45,15 @@ def MRM_D0 : Format<45>;
def MRM_D1 : Format<46>;
def MRM_D4 : Format<47>;
def MRM_D5 : Format<48>;
def MRM_D8 : Format<49>;
def MRM_D9 : Format<50>;
def MRM_DA : Format<51>;
def MRM_DB : Format<52>;
def MRM_DC : Format<53>;
def MRM_DD : Format<54>;
def MRM_DE : Format<55>;
def MRM_DF : Format<56>;
def MRM_D6 : Format<49>;
def MRM_D8 : Format<50>;
def MRM_D9 : Format<51>;
def MRM_DA : Format<52>;
def MRM_DB : Format<53>;
def MRM_DC : Format<54>;
def MRM_DD : Format<55>;
def MRM_DE : Format<56>;
def MRM_DF : Format<57>;
// ImmType - This specifies the immediate type used by an instruction. This is
// part of the ad-hoc solution used to emit machine instruction encodings by our

3
lib/Target/X86/X86InstrTSX.td
View File

@ -27,6 +27,9 @@ def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget:$dst),
def XEND : I<0x01, MRM_D5, (outs), (ins),
"xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
let Defs = [EFLAGS] in
def XTEST : I<0x01, MRM_D6, (outs), (ins), "xtest", []>, TB, Requires<[HasRTM]>;
def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
"xabort\t$imm",
[(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>;

4
test/MC/X86/x86_64-rtm-encoding.s
View File

@ -8,6 +8,10 @@
// CHECK: encoding: [0x0f,0x01,0xd5]
xend
// CHECK: xtest
// CHECK: encoding: [0x0f,0x01,0xd6]
xtest
// CHECK: xabort
// CHECK: encoding: [0xc6,0xf8,0x0d]
xabort $13

17
utils/TableGen/X86RecognizableInstr.cpp
View File

@ -37,14 +37,15 @@ using namespace llvm;
MAP(D1, 46) \
MAP(D4, 47) \
MAP(D5, 48) \
MAP(D8, 49) \
MAP(D9, 50) \
MAP(DA, 51) \
MAP(DB, 52) \
MAP(DC, 53) \
MAP(DD, 54) \
MAP(DE, 55) \
MAP(DF, 56)
MAP(D6, 49) \
MAP(D8, 50) \
MAP(D9, 51) \
MAP(DA, 52) \
MAP(DB, 53) \
MAP(DC, 54) \
MAP(DD, 55) \
MAP(DE, 56) \
MAP(DF, 57)
// A clone of X86 since we can't depend on something that is generated.
namespace X86Local {