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R600/SI: Use eliminateFrameIndex() to expand SGPR spill pseudos
This will simplify the SGPR spilling and also allow us to use MachineFrameInfo for calculating offsets, which should be more reliable than our custom code. This fixes a crash in some cases where a register would be spilled in a branch such that the VGPR defined for spilling did not dominate all the uses when restoring. This fixes a crash in an ocl conformance test. The test requries register spilling and is too big to include. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216217 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -17,6 +17,7 @@
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#include "AMDGPUTargetMachine.h"
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#include "AMDGPUTargetMachine.h"
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#include "SIDefines.h"
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#include "SIDefines.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Function.h"
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@ -401,38 +402,21 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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const TargetRegisterClass *RC,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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const TargetRegisterInfo *TRI) const {
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MachineFunction *MF = MBB.getParent();
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MachineFunction *MF = MBB.getParent();
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SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
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MachineFrameInfo *FrameInfo = MF->getFrameInfo();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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DebugLoc DL = MBB.findDebugLoc(MI);
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DebugLoc DL = MBB.findDebugLoc(MI);
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unsigned KillFlag = isKill ? RegState::Kill : 0;
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if (RI.hasVGPRs(RC)) {
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if (RI.hasVGPRs(RC)) {
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LLVMContext &Ctx = MF->getFunction()->getContext();
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LLVMContext &Ctx = MF->getFunction()->getContext();
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Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
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Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
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BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
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BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
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.addReg(SrcReg);
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.addReg(SrcReg);
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} else if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
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unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF);
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unsigned TgtReg = MFI->SpillTracker.LaneVGPR;
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BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), TgtReg)
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.addReg(SrcReg, KillFlag)
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.addImm(Lane);
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MFI->SpillTracker.addSpilledReg(FrameIndex, TgtReg, Lane);
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} else if (RI.isSGPRClass(RC)) {
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} else if (RI.isSGPRClass(RC)) {
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// We are only allowed to create one new instruction when spilling
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// We are only allowed to create one new instruction when spilling
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// registers, so we need to use pseudo instruction for vector
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// registers, so we need to use pseudo instruction for spilling
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// registers.
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// SGPRs.
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//
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// Reserve a spot in the spill tracker for each sub-register of
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// the vector register.
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unsigned NumSubRegs = RC->getSize() / 4;
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unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MF, NumSubRegs);
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MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
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FirstLane);
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unsigned Opcode;
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unsigned Opcode;
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switch (RC->getSize() * 8) {
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switch (RC->getSize() * 8) {
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case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
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case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
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case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
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case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
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case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
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case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
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case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
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@ -440,9 +424,10 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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default: llvm_unreachable("Cannot spill register class");
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default: llvm_unreachable("Cannot spill register class");
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}
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}
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BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
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FrameInfo->setObjectAlignment(FrameIndex, 4);
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BuildMI(MBB, MI, DL, get(Opcode))
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.addReg(SrcReg)
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.addReg(SrcReg)
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.addImm(FrameIndex);
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.addFrameIndex(FrameIndex);
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} else {
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} else {
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llvm_unreachable("VGPR spilling not supported");
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llvm_unreachable("VGPR spilling not supported");
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}
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}
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@ -454,7 +439,7 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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const TargetRegisterClass *RC,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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const TargetRegisterInfo *TRI) const {
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MachineFunction *MF = MBB.getParent();
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MachineFunction *MF = MBB.getParent();
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SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
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MachineFrameInfo *FrameInfo = MF->getFrameInfo();
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DebugLoc DL = MBB.findDebugLoc(MI);
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DebugLoc DL = MBB.findDebugLoc(MI);
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if (RI.hasVGPRs(RC)) {
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if (RI.hasVGPRs(RC)) {
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@ -473,38 +458,14 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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default: llvm_unreachable("Cannot spill register class");
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default: llvm_unreachable("Cannot spill register class");
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}
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}
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SIMachineFunctionInfo::SpilledReg Spill =
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FrameInfo->setObjectAlignment(FrameIndex, 4);
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MFI->SpillTracker.getSpilledReg(FrameIndex);
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BuildMI(MBB, MI, DL, get(Opcode), DestReg)
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BuildMI(MBB, MI, DL, get(Opcode), DestReg)
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.addReg(Spill.VGPR)
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.addFrameIndex(FrameIndex);
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.addImm(FrameIndex);
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} else {
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} else {
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llvm_unreachable("VGPR spilling not supported");
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llvm_unreachable("VGPR spilling not supported");
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}
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}
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}
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}
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static unsigned getNumSubRegsForSpillOp(unsigned Op) {
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switch (Op) {
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S512_RESTORE:
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return 16;
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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return 8;
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case AMDGPU::SI_SPILL_S128_SAVE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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return 4;
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case AMDGPU::SI_SPILL_S64_SAVE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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return 2;
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case AMDGPU::SI_SPILL_S32_RESTORE:
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return 1;
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default: llvm_unreachable("Invalid spill opcode");
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}
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}
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void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
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void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
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int Count) const {
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int Count) const {
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while (Count > 0) {
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while (Count > 0) {
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@ -520,59 +481,11 @@ void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
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}
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}
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bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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SIMachineFunctionInfo *MFI =
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MI->getParent()->getParent()->getInfo<SIMachineFunctionInfo>();
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MachineBasicBlock &MBB = *MI->getParent();
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MachineBasicBlock &MBB = *MI->getParent();
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DebugLoc DL = MBB.findDebugLoc(MI);
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DebugLoc DL = MBB.findDebugLoc(MI);
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switch (MI->getOpcode()) {
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switch (MI->getOpcode()) {
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default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
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default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
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// SGPR register spill
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S128_SAVE:
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case AMDGPU::SI_SPILL_S64_SAVE: {
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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unsigned FrameIndex = MI->getOperand(2).getImm();
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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SIMachineFunctionInfo::SpilledReg Spill;
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unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
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&AMDGPU::SGPR_32RegClass, i);
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Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
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MI->getOperand(0).getReg())
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.addReg(SubReg)
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.addImm(Spill.Lane + i);
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}
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MI->eraseFromParent();
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break;
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}
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// SGPR register restore
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case AMDGPU::SI_SPILL_S512_RESTORE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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case AMDGPU::SI_SPILL_S32_RESTORE: {
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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SIMachineFunctionInfo::SpilledReg Spill;
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unsigned FrameIndex = MI->getOperand(2).getImm();
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unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
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&AMDGPU::SGPR_32RegClass, i);
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Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
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.addReg(MI->getOperand(1).getReg())
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.addImm(Spill.Lane + i);
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}
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insertNOPs(MI, 3);
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::SI_CONSTDATA_PTR: {
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case AMDGPU::SI_CONSTDATA_PTR: {
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unsigned Reg = MI->getOperand(0).getReg();
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unsigned Reg = MI->getOperand(0).getReg();
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unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
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unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
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@ -1729,14 +1729,14 @@ def V_SUB_F64 : InstSI <
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multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
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multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
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def _SAVE : InstSI <
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def _SAVE : InstSI <
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(outs VReg_32:$dst),
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(outs),
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(ins sgpr_class:$src, i32imm:$frame_idx),
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(ins sgpr_class:$src, i32imm:$frame_idx),
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"", []
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"", []
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>;
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>;
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def _RESTORE : InstSI <
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def _RESTORE : InstSI <
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(outs sgpr_class:$dst),
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(outs sgpr_class:$dst),
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(ins VReg_32:$src, i32imm:$frame_idx),
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(ins i32imm:$frame_idx),
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"", []
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"", []
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>;
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>;
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@ -12,6 +12,7 @@
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#include "SIMachineFunctionInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIInstrInfo.h"
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/LLVMContext.h"
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@ -90,8 +91,49 @@ void SIMachineFunctionInfo::RegSpillTracker::addSpilledReg(unsigned FrameIndex,
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int Lane) {
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int Lane) {
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SpilledRegisters[FrameIndex] = SpilledReg(Reg, Lane);
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SpilledRegisters[FrameIndex] = SpilledReg(Reg, Lane);
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}
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}
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/// \brief Returns a register that is not used at any point in the function.
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/// If all registers are used, then this function will return
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// AMDGPU::NoRegister.
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static unsigned findUnusedVGPR(const MachineRegisterInfo &MRI) {
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const SIMachineFunctionInfo::SpilledReg&
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const TargetRegisterClass *RC = &AMDGPU::VGPR_32RegClass;
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SIMachineFunctionInfo::RegSpillTracker::getSpilledReg(unsigned FrameIndex) {
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return SpilledRegisters[FrameIndex];
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
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I != E; ++I) {
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if (!MRI.isPhysRegUsed(*I))
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return *I;
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}
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return AMDGPU::NoRegister;
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}
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SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
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MachineFunction *MF,
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unsigned FrameIndex,
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unsigned SubIdx) {
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const MachineFrameInfo *FrameInfo = MF->getFrameInfo();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
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Offset += SubIdx * 4;
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unsigned LaneVGPRIdx = Offset / (64 * 4);
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unsigned Lane = (Offset / 4) % 64;
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struct SpilledReg Spill;
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if (!LaneVGPRs.count(LaneVGPRIdx)) {
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unsigned LaneVGPR = findUnusedVGPR(MRI);
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LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
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MRI.setPhysRegUsed(LaneVGPR);
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// Add this register as live-in to all blocks to avoid machine verifer
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// complaining about use of an undefined physical register.
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for (MachineFunction::iterator BI = MF->begin(), BE = MF->end();
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BI != BE; ++BI) {
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BI->addLiveIn(LaneVGPR);
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}
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}
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Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
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Spill.Lane = Lane;
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return Spill;
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}
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}
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@ -57,9 +57,12 @@ public:
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// SIMachineFunctionInfo definition
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// SIMachineFunctionInfo definition
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SIMachineFunctionInfo(const MachineFunction &MF);
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SIMachineFunctionInfo(const MachineFunction &MF);
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SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex,
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unsigned SubIdx);
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unsigned PSInputAddr;
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unsigned PSInputAddr;
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struct RegSpillTracker SpillTracker;
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struct RegSpillTracker SpillTracker;
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unsigned NumUserSGPRs;
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unsigned NumUserSGPRs;
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std::map<unsigned, unsigned> LaneVGPRs;
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};
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};
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} // End namespace llvm
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} // End namespace llvm
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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using namespace llvm;
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using namespace llvm;
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@ -43,23 +45,110 @@ bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const
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return Fn.getFrameInfo()->hasStackObjects();
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return Fn.getFrameInfo()->hasStackObjects();
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}
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}
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static unsigned getNumSubRegsForSpillOp(unsigned Op) {
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switch (Op) {
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S512_RESTORE:
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return 16;
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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return 8;
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case AMDGPU::SI_SPILL_S128_SAVE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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return 4;
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case AMDGPU::SI_SPILL_S64_SAVE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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return 2;
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case AMDGPU::SI_SPILL_S32_SAVE:
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case AMDGPU::SI_SPILL_S32_RESTORE:
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return 1;
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default: llvm_unreachable("Invalid spill opcode");
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}
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}
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void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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int SPAdj, unsigned FIOperandNum,
|
||||||
RegScavenger *RS) const {
|
RegScavenger *RS) const {
|
||||||
MachineFunction *MF = MI->getParent()->getParent();
|
MachineFunction *MF = MI->getParent()->getParent();
|
||||||
|
MachineBasicBlock *MBB = MI->getParent();
|
||||||
|
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
|
||||||
MachineFrameInfo *FrameInfo = MF->getFrameInfo();
|
MachineFrameInfo *FrameInfo = MF->getFrameInfo();
|
||||||
const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
|
const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
|
||||||
|
DebugLoc DL = MI->getDebugLoc();
|
||||||
|
|
||||||
MachineOperand &FIOp = MI->getOperand(FIOperandNum);
|
MachineOperand &FIOp = MI->getOperand(FIOperandNum);
|
||||||
int Index = MI->getOperand(FIOperandNum).getIndex();
|
int Index = MI->getOperand(FIOperandNum).getIndex();
|
||||||
int64_t Offset = FrameInfo->getObjectOffset(Index);
|
|
||||||
|
|
||||||
FIOp.ChangeToImmediate(Offset);
|
switch (MI->getOpcode()) {
|
||||||
if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
|
// SGPR register spill
|
||||||
unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VReg_32RegClass, MI, SPAdj);
|
case AMDGPU::SI_SPILL_S512_SAVE:
|
||||||
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
|
case AMDGPU::SI_SPILL_S256_SAVE:
|
||||||
TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
|
case AMDGPU::SI_SPILL_S128_SAVE:
|
||||||
.addImm(Offset);
|
case AMDGPU::SI_SPILL_S64_SAVE:
|
||||||
FIOp.ChangeToRegister(TmpReg, false);
|
case AMDGPU::SI_SPILL_S32_SAVE: {
|
||||||
|
unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
|
||||||
|
|
||||||
|
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
|
||||||
|
unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
|
||||||
|
&AMDGPU::SGPR_32RegClass, i);
|
||||||
|
struct SIMachineFunctionInfo::SpilledReg Spill =
|
||||||
|
MFI->getSpilledReg(MF, Index, i);
|
||||||
|
|
||||||
|
if (Spill.VGPR == AMDGPU::NoRegister) {
|
||||||
|
LLVMContext &Ctx = MF->getFunction()->getContext();
|
||||||
|
Ctx.emitError("Ran out of VGPRs for spilling SGPR");
|
||||||
|
}
|
||||||
|
|
||||||
|
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR)
|
||||||
|
.addReg(SubReg)
|
||||||
|
.addImm(Spill.Lane);
|
||||||
|
|
||||||
|
}
|
||||||
|
MI->eraseFromParent();
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
// SGPR register restore
|
||||||
|
case AMDGPU::SI_SPILL_S512_RESTORE:
|
||||||
|
case AMDGPU::SI_SPILL_S256_RESTORE:
|
||||||
|
case AMDGPU::SI_SPILL_S128_RESTORE:
|
||||||
|
case AMDGPU::SI_SPILL_S64_RESTORE:
|
||||||
|
case AMDGPU::SI_SPILL_S32_RESTORE: {
|
||||||
|
unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
|
||||||
|
|
||||||
|
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
|
||||||
|
unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
|
||||||
|
&AMDGPU::SGPR_32RegClass, i);
|
||||||
|
struct SIMachineFunctionInfo::SpilledReg Spill =
|
||||||
|
MFI->getSpilledReg(MF, Index, i);
|
||||||
|
|
||||||
|
if (Spill.VGPR == AMDGPU::NoRegister) {
|
||||||
|
LLVMContext &Ctx = MF->getFunction()->getContext();
|
||||||
|
Ctx.emitError("Ran out of VGPRs for spilling SGPR");
|
||||||
|
}
|
||||||
|
|
||||||
|
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
|
||||||
|
.addReg(Spill.VGPR)
|
||||||
|
.addImm(Spill.Lane);
|
||||||
|
|
||||||
|
}
|
||||||
|
TII->insertNOPs(MI, 3);
|
||||||
|
MI->eraseFromParent();
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
default: {
|
||||||
|
int64_t Offset = FrameInfo->getObjectOffset(Index);
|
||||||
|
FIOp.ChangeToImmediate(Offset);
|
||||||
|
if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
|
||||||
|
unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VReg_32RegClass, MI, SPAdj);
|
||||||
|
BuildMI(*MBB, MI, MI->getDebugLoc(),
|
||||||
|
TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
|
||||||
|
.addImm(Offset);
|
||||||
|
FIOp.ChangeToRegister(TmpReg, false);
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user