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Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24683 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2005-12-13 00:14:11 +00:00
parent b3558540b6
commit 9b6b642647
1 changed files with 47 additions and 34 deletions
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81
lib/Target/X86/X86InstrInfo.td
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@ -143,20 +143,20 @@ class XS { bits<4> Prefix = 12; }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pattern fragments... // Pattern fragments...
// //
def i16SExt8 : PatLeaf<(i16 imm), [{ def i16immSExt8 : PatLeaf<(i16 imm), [{
// i16SExt8 predicate - True if the 16-bit immediate fits in a 8-bit // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
// sign extended field. // sign extended field.
return (int)N->getValue() == (signed char)N->getValue(); return (int)N->getValue() == (signed char)N->getValue();
}]>; }]>;
def i32SExt8 : PatLeaf<(i32 imm), [{ def i32immSExt8 : PatLeaf<(i32 imm), [{
// i32SExt8 predicate - True if the 32-bit immediate fits in a 8-bit // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
// sign extended field. // sign extended field.
return (int)N->getValue() == (signed char)N->getValue(); return (int)N->getValue() == (signed char)N->getValue();
}]>; }]>;
def i16ZExt8 : PatLeaf<(i16 imm), [{ def i16immZExt8 : PatLeaf<(i16 imm), [{
// i16ZExt8 predicate - True if the 16-bit immediate fits in a 8-bit zero // i16immZExt8 predicate - True if the 16-bit immediate fits in a 8-bit zero
// extended field. // extended field.
return (unsigned)N->getValue() == (unsigned char)N->getValue(); return (unsigned)N->getValue() == (unsigned char)N->getValue();
}]>; }]>;
@ -354,15 +354,15 @@ def OUT32rr : I<0xEF, RawFrm, (ops),
def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port), def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
"out{b} {%al, $port|$port, %AL}", "out{b} {%al, $port|$port, %AL}",
[(writeport AL, (i16 i16ZExt8:$port))]>, [(writeport AL, (i16 i16immZExt8:$port))]>,
Imp<[AL], []>; Imp<[AL], []>;
def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
"out{w} {%ax, $port|$port, %AX}", "out{w} {%ax, $port|$port, %AX}",
[(writeport AX, (i16 i16ZExt8:$port))]>, [(writeport AX, (i16 i16immZExt8:$port))]>,
Imp<[AX], []>, OpSize; Imp<[AX], []>, OpSize;
def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
"out{l} {%eax, $port|$port, %EAX}", "out{l} {%eax, $port|$port, %EAX}",
[(writeport EAX, (i16 i16ZExt8:$port))]>, [(writeport EAX, (i16 i16immZExt8:$port))]>,
Imp<[EAX], []>; Imp<[EAX], []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -770,11 +770,12 @@ def AND32ri : Ii32<0x81, MRM4r,
def AND16ri8 : Ii8<0x83, MRM4r, def AND16ri8 : Ii8<0x83, MRM4r,
(ops R16:$dst, R16:$src1, i16i8imm:$src2), (ops R16:$dst, R16:$src1, i16i8imm:$src2),
"and{w} {$src2, $dst|$dst, $src2}", "and{w} {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (and R16:$src1, i16SExt8:$src2))]>, OpSize; [(set R16:$dst, (and R16:$src1, i16immSExt8:$src2))]>,
OpSize;
def AND32ri8 : Ii8<0x83, MRM4r, def AND32ri8 : Ii8<0x83, MRM4r,
(ops R32:$dst, R32:$src1, i32i8imm:$src2), (ops R32:$dst, R32:$src1, i32i8imm:$src2),
"and{l} {$src2, $dst|$dst, $src2}", "and{l} {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (and R32:$src1, i32SExt8:$src2))]>; [(set R32:$dst, (and R32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in { let isTwoAddress = 0 in {
def AND8mr : I<0x20, MRMDestMem, def AND8mr : I<0x20, MRMDestMem,
@ -834,10 +835,10 @@ def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
"or{w} {$src2, $dst|$dst, $src2}", "or{w} {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (or R16:$src1, i16SExt8:$src2))]>, OpSize; [(set R16:$dst, (or R16:$src1, i16immSExt8:$src2))]>, OpSize;
def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
"or{l} {$src2, $dst|$dst, $src2}", "or{l} {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (or R32:$src1, i32SExt8:$src2))]>; [(set R32:$dst, (or R32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in { let isTwoAddress = 0 in {
def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src), def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
"or{b} {$src, $dst|$dst, $src}", []>; "or{b} {$src, $dst|$dst, $src}", []>;
@ -898,11 +899,12 @@ def XOR32ri : Ii32<0x81, MRM6r,
def XOR16ri8 : Ii8<0x83, MRM6r, def XOR16ri8 : Ii8<0x83, MRM6r,
(ops R16:$dst, R16:$src1, i16i8imm:$src2), (ops R16:$dst, R16:$src1, i16i8imm:$src2),
"xor{w} {$src2, $dst|$dst, $src2}", "xor{w} {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (xor R16:$src1, i16SExt8:$src2))]>, OpSize; [(set R16:$dst, (xor R16:$src1, i16immSExt8:$src2))]>,
OpSize;
def XOR32ri8 : Ii8<0x83, MRM6r, def XOR32ri8 : Ii8<0x83, MRM6r,
(ops R32:$dst, R32:$src1, i32i8imm:$src2), (ops R32:$dst, R32:$src1, i32i8imm:$src2),
"xor{l} {$src2, $dst|$dst, $src2}", "xor{l} {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (xor R32:$src1, i32SExt8:$src2))]>; [(set R32:$dst, (xor R32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in { let isTwoAddress = 0 in {
def XOR8mr : I<0x30, MRMDestMem, def XOR8mr : I<0x30, MRMDestMem,
(ops i8mem :$dst, R8 :$src), (ops i8mem :$dst, R8 :$src),
@ -1205,10 +1207,11 @@ def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
// FIXME: move ADD16ri8 above ADD16ri to optimize for space. // FIXME: move ADD16ri8 above ADD16ri to optimize for space.
def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
"add{w} {$src2, $dst|$dst, $src2}", "add{w} {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (add R16:$src1, i16SExt8:$src2))]>, OpSize; [(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>,
OpSize;
def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
"add{l} {$src2, $dst|$dst, $src2}", "add{l} {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (add R32:$src1, i32SExt8:$src2))]>; [(set R32:$dst, (add R32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in { let isTwoAddress = 0 in {
def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2), def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
@ -1216,7 +1219,8 @@ let isTwoAddress = 0 in {
[(store (add (load addr:$dst), R8:$src2), addr:$dst)]>; [(store (add (load addr:$dst), R8:$src2), addr:$dst)]>;
def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2), def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2),
"add{w} {$src2, $dst|$dst, $src2}", "add{w} {$src2, $dst|$dst, $src2}",
[(store (add (load addr:$dst), R16:$src2), addr:$dst)]>, OpSize; [(store (add (load addr:$dst), R16:$src2), addr:$dst)]>,
OpSize;
def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2), def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2),
"add{l} {$src2, $dst|$dst, $src2}", "add{l} {$src2, $dst|$dst, $src2}",
[(store (add (load addr:$dst), R32:$src2), addr:$dst)]>; [(store (add (load addr:$dst), R32:$src2), addr:$dst)]>;
@ -1225,16 +1229,18 @@ let isTwoAddress = 0 in {
[(store (add (load addr:$dst), (i8 imm:$src2)), addr:$dst)]>; [(store (add (load addr:$dst), (i8 imm:$src2)), addr:$dst)]>;
def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
"add{w} {$src2, $dst|$dst, $src2}", "add{w} {$src2, $dst|$dst, $src2}",
[(store (add (load addr:$dst), (i16 imm:$src2)), addr:$dst)]>, OpSize; [(store (add (load addr:$dst), (i16 imm:$src2)), addr:$dst)]>,
OpSize;
def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
"add{l} {$src2, $dst|$dst, $src2}", "add{l} {$src2, $dst|$dst, $src2}",
[(store (add (load addr:$dst), (i32 imm:$src2)), addr:$dst)]>; [(store (add (load addr:$dst), (i32 imm:$src2)), addr:$dst)]>;
def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2), def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2),
"add{w} {$src2, $dst|$dst, $src2}", "add{w} {$src2, $dst|$dst, $src2}",
[(store (add (load addr:$dst), i16SExt8:$src2), addr:$dst)]>, OpSize; [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
OpSize;
def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2), def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2),
"add{l} {$src2, $dst|$dst, $src2}", "add{l} {$src2, $dst|$dst, $src2}",
[(store (add (load addr:$dst), i32SExt8:$src2), addr:$dst)]>; [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
} }
let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
@ -1287,17 +1293,19 @@ def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
[(set R32:$dst, (sub R32:$src1, imm:$src2))]>; [(set R32:$dst, (sub R32:$src1, imm:$src2))]>;
def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
"sub{w} {$src2, $dst|$dst, $src2}", "sub{w} {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (sub R16:$src1, i16SExt8:$src2))]>, OpSize; [(set R16:$dst, (sub R16:$src1, i16immSExt8:$src2))]>,
OpSize;
def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
"sub{l} {$src2, $dst|$dst, $src2}", "sub{l} {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (sub R32:$src1, i32SExt8:$src2))]>; [(set R32:$dst, (sub R32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in { let isTwoAddress = 0 in {
def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2), def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
"sub{b} {$src2, $dst|$dst, $src2}", "sub{b} {$src2, $dst|$dst, $src2}",
[(store (sub (load addr:$dst), R8:$src2), addr:$dst)]>; [(store (sub (load addr:$dst), R8:$src2), addr:$dst)]>;
def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2), def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2),
"sub{w} {$src2, $dst|$dst, $src2}", "sub{w} {$src2, $dst|$dst, $src2}",
[(store (sub (load addr:$dst), R16:$src2), addr:$dst)]>, OpSize; [(store (sub (load addr:$dst), R16:$src2), addr:$dst)]>,
OpSize;
def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2),
"sub{l} {$src2, $dst|$dst, $src2}", "sub{l} {$src2, $dst|$dst, $src2}",
[(store (sub (load addr:$dst), R32:$src2), addr:$dst)]>; [(store (sub (load addr:$dst), R32:$src2), addr:$dst)]>;
@ -1306,16 +1314,18 @@ let isTwoAddress = 0 in {
[(store (sub (load addr:$dst), (i8 imm:$src2)), addr:$dst)]>; [(store (sub (load addr:$dst), (i8 imm:$src2)), addr:$dst)]>;
def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
"sub{w} {$src2, $dst|$dst, $src2}", "sub{w} {$src2, $dst|$dst, $src2}",
[(store (sub (load addr:$dst), (i16 imm:$src2)), addr:$dst)]>, OpSize; [(store (sub (load addr:$dst), (i16 imm:$src2)), addr:$dst)]>,
OpSize;
def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
"sub{l} {$src2, $dst|$dst, $src2}", "sub{l} {$src2, $dst|$dst, $src2}",
[(store (sub (load addr:$dst), (i32 imm:$src2)), addr:$dst)]>; [(store (sub (load addr:$dst), (i32 imm:$src2)), addr:$dst)]>;
def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2), def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2),
"sub{w} {$src2, $dst|$dst, $src2}", "sub{w} {$src2, $dst|$dst, $src2}",
[(store (sub (load addr:$dst), i16SExt8:$src2), addr:$dst)]>, OpSize; [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
OpSize;
def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2), def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2),
"sub{l} {$src2, $dst|$dst, $src2}", "sub{l} {$src2, $dst|$dst, $src2}",
[(store (sub (load addr:$dst), i32SExt8:$src2), addr:$dst)]>; [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
} }
def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
@ -1360,7 +1370,8 @@ def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
} }
def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
"imul{w} {$src2, $dst|$dst, $src2}", "imul{w} {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (mul R16:$src1, (load addr:$src2)))]>, TB, OpSize; [(set R16:$dst, (mul R16:$src1, (load addr:$src2)))]>,
TB, OpSize;
def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
"imul{l} {$src2, $dst|$dst, $src2}", "imul{l} {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (mul R32:$src1, (load addr:$src2)))]>, TB; [(set R32:$dst, (mul R32:$src1, (load addr:$src2)))]>, TB;
@ -1379,11 +1390,12 @@ def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32
def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8
(ops R16:$dst, R16:$src1, i16i8imm:$src2), (ops R16:$dst, R16:$src1, i16i8imm:$src2),
"imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
[(set R16:$dst, (mul R16:$src1, i16SExt8:$src2))]>, OpSize; [(set R16:$dst, (mul R16:$src1, i16immSExt8:$src2))]>,
OpSize;
def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8
(ops R32:$dst, R32:$src1, i32i8imm:$src2), (ops R32:$dst, R32:$src1, i32i8imm:$src2),
"imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
[(set R32:$dst, (mul R32:$src1, i32SExt8:$src2))]>; [(set R32:$dst, (mul R32:$src1, i32immSExt8:$src2))]>;
def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16
(ops R16:$dst, i16mem:$src1, i16imm:$src2), (ops R16:$dst, i16mem:$src1, i16imm:$src2),
@ -1397,11 +1409,12 @@ def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32
def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8
(ops R16:$dst, i16mem:$src1, i16i8imm :$src2), (ops R16:$dst, i16mem:$src1, i16i8imm :$src2),
"imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
[(set R16:$dst, (mul (load addr:$src1), i16SExt8:$src2))]>, OpSize; [(set R16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
OpSize;
def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8
(ops R32:$dst, i32mem:$src1, i32i8imm: $src2), (ops R32:$dst, i32mem:$src1, i32i8imm: $src2),
"imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
[(set R32:$dst, (mul (load addr:$src1), i32SExt8:$src2))]>; [(set R32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Test instructions are just like AND, except they don't generate a result. // Test instructions are just like AND, except they don't generate a result.