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Adjust to new TargetMachine interface

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13956 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2004-06-02 05:57:12 +00:00
parent 62d6ad2cee
commit 9bcdcd17c7
11 changed files with 18 additions and 19 deletions
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4
lib/CodeGen/RegAllocSimple.cpp
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@ -159,7 +159,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses)
unsigned Opcode = MI->getOpcode();
const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
const unsigned *Regs = Desc.ImplicitUses;
while (*Regs)
RegsUsed[*Regs++] = true;
@ -184,7 +184,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
if (!TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) || i) {
if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
physReg = getFreeReg(virtualReg);
} else {
// must be same register number as the first operand