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The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137151 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2011-08-09 21:34:19 +00:00
parent ad0d36b79f
commit 9bd7c2836e
1 changed files with 0 additions and 10 deletions
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10
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
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@ -165,11 +165,6 @@ namespace {
class ARMMCInstrAnalysis : public MCInstrAnalysis {
public:
ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
virtual bool isBranch(const MCInst &Inst) const {
// Don't flag "bx lr" as a branch.
return MCInstrAnalysis::isBranch(Inst) && (Inst.getOpcode() != ARM::BX ||
Inst.getOperand(0).getReg() != ARM::LR);
}
virtual bool isUnconditionalBranch(const MCInst &Inst) const {
// BCCs with the "always" predicate are unconditional branches.
@ -185,11 +180,6 @@ public:
return MCInstrAnalysis::isConditionalBranch(Inst);
}
virtual bool isReturn(const MCInst &Inst) const {
// Recognize "bx lr" as return.
return Inst.getOpcode() == ARM::BX && Inst.getOperand(0).getReg()==ARM::LR;
}
uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
uint64_t Size) const {
// We only handle PCRel branches for now.