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Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb

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The current patterns for REV16 misses mostn __builtin_bswap16() due to
legalization promoting the operands to from load/stores toi32s and then
truncing/extending them. This patch adds new patterns that catch the resultant
DAGs and codegens them to rev16 instructions. Tests included.

rdar://15353652

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208620 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Louis Gerbarg 2014-05-12 19:53:52 +00:00
parent b36e348af3
commit 9cec62a27f
3 changed files with 59 additions and 0 deletions
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5
lib/Target/ARM/ARMInstrInfo.td
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@ -4122,6 +4122,11 @@ def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
Requires<[IsARM, HasV6]>, Requires<[IsARM, HasV6]>,
Sched<[WriteALU]>; Sched<[WriteALU]>;
def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
(REV16 (LDRH addrmode3:$addr))>;
def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
(STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
let AddedComplexity = 5 in let AddedComplexity = 5 in
def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
IIC_iUNAr, "revsh", "\t$Rd, $Rm", IIC_iUNAr, "revsh", "\t$Rd, $Rm",

12
lib/Target/ARM/ARMInstrThumb.td
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@ -1308,6 +1308,18 @@ def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
(tSUBrr tGPR:$lhs, tGPR:$rhs)>; (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
// Bswap 16 with load/store
def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rrs2:$addr)), (i32 16)),
(tREV16 (tLDRHr t_addrmode_rrs2:$addr))>;
def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),
(tREV16 (tLDRHi t_addrmode_is2:$addr))>;
def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
t_addrmode_rrs2:$addr),
(tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rrs2:$addr)>;
def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
t_addrmode_is2:$addr),
(tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>;
// ConstantPool // ConstantPool
def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;

42
test/CodeGen/ARM/bswap16.ll Normal file
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@ -0,0 +1,42 @@
; RUN: llc -march=arm -mattr=v6 < %s | FileCheck %s
; RUN: llc -march=thumb -mattr=v6 < %s | FileCheck %s
define void @test1(i16* nocapture %data) {
entry:
%0 = load i16* %data, align 2
%1 = tail call i16 @llvm.bswap.i16(i16 %0)
store i16 %1, i16* %data, align 2
ret void
; CHECK-LABEL: test1:
; CHECK: ldrh r[[R1:[0-9]+]], [r0]
; CHECK: rev16 r[[R1]], r[[R1]]
; CHECK: strh r[[R1]], [r0]
}
define void @test2(i16* nocapture %data, i16 zeroext %in) {
entry:
%0 = tail call i16 @llvm.bswap.i16(i16 %in)
store i16 %0, i16* %data, align 2
ret void
; CHECK-LABEL: test2:
; CHECK: rev16 r[[R1:[0-9]+]], r1
; CHECK: strh r[[R1]], [r0]
}
define i16 @test3(i16* nocapture %data) {
entry:
%0 = load i16* %data, align 2
%1 = tail call i16 @llvm.bswap.i16(i16 %0)
ret i16 %1
; CHECK-LABEL: test3:
; CHECK: ldrh r[[R0:[0-9]+]], [r0]
; CHECK: rev16 r[[R0]], r0
}
declare i16 @llvm.bswap.i16(i16)