llvm-6502/test/CodeGen/ARM/bswap16.ll
Louis Gerbarg 9cec62a27f Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb
The current patterns for REV16 misses mostn __builtin_bswap16() due to
legalization promoting the operands to from load/stores toi32s and then
truncing/extending them. This patch adds new patterns that catch the resultant
DAGs and codegens them to rev16 instructions. Tests included.

rdar://15353652

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208620 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 19:53:52 +00:00

43 lines
935 B
LLVM

; RUN: llc -march=arm -mattr=v6 < %s | FileCheck %s
; RUN: llc -march=thumb -mattr=v6 < %s | FileCheck %s
define void @test1(i16* nocapture %data) {
entry:
%0 = load i16* %data, align 2
%1 = tail call i16 @llvm.bswap.i16(i16 %0)
store i16 %1, i16* %data, align 2
ret void
; CHECK-LABEL: test1:
; CHECK: ldrh r[[R1:[0-9]+]], [r0]
; CHECK: rev16 r[[R1]], r[[R1]]
; CHECK: strh r[[R1]], [r0]
}
define void @test2(i16* nocapture %data, i16 zeroext %in) {
entry:
%0 = tail call i16 @llvm.bswap.i16(i16 %in)
store i16 %0, i16* %data, align 2
ret void
; CHECK-LABEL: test2:
; CHECK: rev16 r[[R1:[0-9]+]], r1
; CHECK: strh r[[R1]], [r0]
}
define i16 @test3(i16* nocapture %data) {
entry:
%0 = load i16* %data, align 2
%1 = tail call i16 @llvm.bswap.i16(i16 %0)
ret i16 %1
; CHECK-LABEL: test3:
; CHECK: ldrh r[[R0:[0-9]+]], [r0]
; CHECK: rev16 r[[R0]], r0
}
declare i16 @llvm.bswap.i16(i16)