remove TargetMachine.h #include, also, TRI isn't used frequently

enough to warrant caching in AsmPrinter, so remove it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100336 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-04-04 18:06:11 +00:00
parent bbef815a3b
commit 9d1c1ada21
7 changed files with 14 additions and 14 deletions

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@ -18,7 +18,6 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Support/DebugLoc.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class BlockAddress;
@ -84,10 +83,6 @@ namespace llvm {
///
const MCAsmInfo *MAI;
/// Target Register Information.
///
const TargetRegisterInfo *TRI;
/// OutContext - This is the context for the output file that we are
/// streaming. This owns all of the global MC-related objects for the
/// generated translation unit.

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@ -65,7 +65,7 @@ static gcp_map_type &getGCMap(void *&P) {
AsmPrinter::AsmPrinter(TargetMachine &tm, MCStreamer &Streamer)
: MachineFunctionPass(&ID),
TM(tm), MAI(tm.getMCAsmInfo()), TRI(tm.getRegisterInfo()),
TM(tm), MAI(tm.getMCAsmInfo()),
OutContext(Streamer.getContext()),
OutStreamer(Streamer),
LastMI(0), LastFn(0), Counter(~0U), SetCounter(0) {
@ -1610,8 +1610,9 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
/// that is an implicit def.
void AsmPrinter::printImplicitDef(const MachineInstr *MI) const {
if (!VerboseAsm) return;
unsigned RegNo = MI->getOperand(0).getReg();
OutStreamer.AddComment(Twine("implicit-def: ") +
TRI->getName(MI->getOperand(0).getReg()));
TM.getRegisterInfo()->getName(RegNo));
OutStreamer.AddBlankLine();
}
@ -1623,7 +1624,7 @@ void AsmPrinter::printKill(const MachineInstr *MI) const {
const MachineOperand &Op = MI->getOperand(n);
assert(Op.isReg() && "KILL instruction must have only register operands");
Str += ' ';
Str += TRI->getName(Op.getReg());
Str += TM.getRegisterInfo()->getName(Op.getReg());
Str += (Op.isDef() ? "<def>" : "<kill>");
}
OutStreamer.AddComment(Str);

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@ -24,6 +24,7 @@
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"

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@ -27,6 +27,7 @@
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Support/Dwarf.h"

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@ -26,6 +26,7 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Dwarf.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/ADT/SmallString.h"

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@ -320,15 +320,16 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
unsigned Reg = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
if (Modifier && strcmp(Modifier, "dregpair") == 0) {
unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, 5);// arm_dsubreg_0
unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, 6);// arm_dsubreg_1
O << '{'
<< getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
<< '}';
} else if (Modifier && strcmp(Modifier, "lane") == 0) {
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
&ARM::DPR_VFP2RegClass);
unsigned DReg =
TM.getRegisterInfo()->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
&ARM::DPR_VFP2RegClass);
O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
} else {
assert(!MO.getSubReg() && "Subregs should be eliminated!");

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@ -130,9 +130,9 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", 6) == 0) {
if (strncmp(Modifier + 7, "even", 4) == 0)
Reg = TRI->getSubReg(Reg, SystemZ::SUBREG_EVEN);
Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::SUBREG_EVEN);
else if (strncmp(Modifier + 7, "odd", 3) == 0)
Reg = TRI->getSubReg(Reg, SystemZ::SUBREG_ODD);
Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::SUBREG_ODD);
else
assert(0 && "Invalid subreg modifier");
}