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https://github.com/c64scene-ar/llvm-6502.git
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remove TargetMachine.h #include, also, TRI isn't used frequently
enough to warrant caching in AsmPrinter, so remove it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100336 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -18,7 +18,6 @@
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/DebugLoc.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class BlockAddress;
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@ -84,10 +83,6 @@ namespace llvm {
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///
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const MCAsmInfo *MAI;
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/// Target Register Information.
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///
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const TargetRegisterInfo *TRI;
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/// OutContext - This is the context for the output file that we are
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/// streaming. This owns all of the global MC-related objects for the
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/// generated translation unit.
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@ -65,7 +65,7 @@ static gcp_map_type &getGCMap(void *&P) {
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AsmPrinter::AsmPrinter(TargetMachine &tm, MCStreamer &Streamer)
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: MachineFunctionPass(&ID),
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TM(tm), MAI(tm.getMCAsmInfo()), TRI(tm.getRegisterInfo()),
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TM(tm), MAI(tm.getMCAsmInfo()),
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OutContext(Streamer.getContext()),
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OutStreamer(Streamer),
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LastMI(0), LastFn(0), Counter(~0U), SetCounter(0) {
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@ -1610,8 +1610,9 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
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/// that is an implicit def.
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void AsmPrinter::printImplicitDef(const MachineInstr *MI) const {
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if (!VerboseAsm) return;
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unsigned RegNo = MI->getOperand(0).getReg();
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OutStreamer.AddComment(Twine("implicit-def: ") +
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TRI->getName(MI->getOperand(0).getReg()));
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TM.getRegisterInfo()->getName(RegNo));
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OutStreamer.AddBlankLine();
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}
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@ -1623,7 +1624,7 @@ void AsmPrinter::printKill(const MachineInstr *MI) const {
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const MachineOperand &Op = MI->getOperand(n);
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assert(Op.isReg() && "KILL instruction must have only register operands");
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Str += ' ';
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Str += TRI->getName(Op.getReg());
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Str += TM.getRegisterInfo()->getName(Op.getReg());
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Str += (Op.isDef() ? "<def>" : "<kill>");
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}
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OutStreamer.AddComment(Str);
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@ -24,6 +24,7 @@
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringExtras.h"
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@ -27,6 +27,7 @@
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Dwarf.h"
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@ -26,6 +26,7 @@
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Dwarf.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/ADT/SmallString.h"
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@ -320,15 +320,16 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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unsigned Reg = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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if (Modifier && strcmp(Modifier, "dregpair") == 0) {
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unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
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unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
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unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, 5);// arm_dsubreg_0
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unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, 6);// arm_dsubreg_1
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O << '{'
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<< getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
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<< '}';
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} else if (Modifier && strcmp(Modifier, "lane") == 0) {
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unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
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unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
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&ARM::DPR_VFP2RegClass);
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unsigned DReg =
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TM.getRegisterInfo()->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
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&ARM::DPR_VFP2RegClass);
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O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
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} else {
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assert(!MO.getSubReg() && "Subregs should be eliminated!");
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@ -130,9 +130,9 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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unsigned Reg = MO.getReg();
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if (Modifier && strncmp(Modifier, "subreg", 6) == 0) {
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if (strncmp(Modifier + 7, "even", 4) == 0)
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Reg = TRI->getSubReg(Reg, SystemZ::SUBREG_EVEN);
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Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::SUBREG_EVEN);
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else if (strncmp(Modifier + 7, "odd", 3) == 0)
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Reg = TRI->getSubReg(Reg, SystemZ::SUBREG_ODD);
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Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::SUBREG_ODD);
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else
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assert(0 && "Invalid subreg modifier");
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}
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