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[XCore] Add missing 1r instructions.
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -853,9 +853,6 @@ def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
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[(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
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// One operand short
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// TODO edu, eeu, waitet, waitef, tstart, clrtp
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// setdp, setcp, setev, kcall
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// dgetreg
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def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
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"msync res[$a]",
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[(int_xcore_msync GRRegs:$a)]>;
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@ -879,9 +876,13 @@ def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
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[(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
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let Defs=[SP], neverHasSideEffects=1 in
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def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a),
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"set sp, $a",
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[]>;
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def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>;
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let neverHasSideEffects=1 in
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def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>;
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let neverHasSideEffects=1 in
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def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>;
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let hasCtrlDep = 1 in
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def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
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@ -919,10 +920,24 @@ def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
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[(int_xcore_setev GRRegs:$a, R11)]>;
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}
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def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>;
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def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>;
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def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
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"eeu res[$a]",
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[(int_xcore_eeu GRRegs:$a)]>;
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def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>;
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def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>;
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def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>;
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def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>;
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def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>;
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// Zero operand short
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def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
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@ -110,6 +110,33 @@
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# CHECK: eeu res[r11]
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0xfb 0x07
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# CHECK: set dp, r5
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0xe5 0x37
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# CHECK: set cp, r0
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0xf0 0x37
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# CHECK: dgetreg r11
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0xeb 0x3f
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# CHECK: edu res[r8]
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0xe8 0x07
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# CHECK: kcall r2
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0xe2 0x47
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# CHECK: waitef r10
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0xfa 0x0f
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# CHECK: waitet r7
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0xe7 0x0f
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# CHECK: start t[r4]
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0xe4 0x1f
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# CHECK: clrpt res[r9]
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0xe9 0x87
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# 2r instructions
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# CHECK: not r1, r8
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