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Do the right thing and enable 64 bit regs under the control of a subtarget

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option.  Currently the only way to enable this is to specify the
64bitregs mattr flag.  It is never enabled by default on any config yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23779 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
2005-10-18 00:56:42 +00:00
parent 1d9d7427c4
commit 9d2b817fcb
3 changed files with 10 additions and 8 deletions
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13
lib/Target/PowerPC/PPCISelLowering.cpp
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@@ -94,19 +94,16 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
// 64 bit PowerPC implementations can support i64 types directly
// FIXME: enable this once it works.
//addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
// They also have instructions for converting between i64 and fp.
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
}
if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
// 64 bit PowerPC implementations can support i64 types directly
addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
// 32 bit PowerPC wants to expand i64 shifts itself.
// FIXME: remove these once we natively handle i64 shifts.
setOperationAction(ISD::SHL, MVT::i64, Custom);
setOperationAction(ISD::SRL, MVT::i64, Custom);
setOperationAction(ISD::SRA, MVT::i64, Custom);
} else {
// 32 bit PowerPC wants to expand i64 shifts itself.
setOperationAction(ISD::SHL, MVT::i64, Custom);