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The Mips specific function for instruction cache invalidation cannot be
compiled on mips32r1 processors because it uses synci and rdhwr instructions which are supported only on mips32r2, so I replaced this function with the call to function cacheflush which works for both mips32r1 and mips32r2. Patch by Sasa Stankovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141564 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -16,6 +16,10 @@
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#include "llvm/Support/Valgrind.h"
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#include "llvm/Config/config.h"
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#if defined(__mips__)
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#include <sys/cachectl.h>
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#endif
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namespace llvm {
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using namespace sys;
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}
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@ -30,39 +34,6 @@ using namespace sys;
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extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
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/// ClearMipsCache - Invalidates instruction cache for Mips. This assembly code
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/// is copied from the MIPS32 Instruction Set Reference. Since the code ends
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/// with the return instruction "jr.hb ra" (Jump Register with Hazard Barrier),
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/// it must be implemented as a function (which is called from the
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/// InvalidateInstructionCache function). It cannot be directly inlined into
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/// InvalidateInstructionCache function, because in that case the epilog of
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/// InvalidateInstructionCache will not be executed.
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#if defined(__mips__)
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extern "C" void ClearMipsCache(const void* Addr, size_t Size);
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asm volatile(
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".text\n"
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".align 2\n"
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".globl ClearMipsCache\n"
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"ClearMipsCache:\n"
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".set noreorder\n"
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"beq $a1, $zero, 20f\n" /* If size==0, branch around */
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"nop\n"
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"addu $a1, $a0, $a1\n" /* Calculate end address + 1 */
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"rdhwr $v0, $1\n" /* Get step size for SYNCI */
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/* $1 is $HW_SYNCI_Step */
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"beq $v0, $zero, 20f\n" /* If no caches require synchronization, */
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/* branch around */
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"nop\n"
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"10: synci 0($a0)\n" /* Synchronize all caches around address */
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"sltu $v1, $a0, $a1\n" /* Compare current with end address */
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"bne $v1, $zero, 10b\n" /* Branch if more to do */
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"addu $a0, $a0, $v0\n" /* Add step size in delay slot */
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"sync\n" /* Clear memory hazards */
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"20: jr.hb $ra\n" /* Return, clearing instruction hazards */
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"nop\n"
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);
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#endif
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/// InvalidateInstructionCache - Before the JIT can run a block of code
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/// that has been emitted it must invalidate the instruction cache on some
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/// platforms.
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@ -100,7 +71,7 @@ void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr,
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char *End = Start + Len;
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__clear_cache(Start, End);
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# elif defined(__mips__)
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ClearMipsCache(Addr, Len);
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cacheflush((char*)Addr, Len, BCACHE);
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# endif
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#endif // end apple
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