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The Mips specific function for instruction cache invalidation cannot be

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compiled on mips32r1 processors because it uses synci and rdhwr instructions
which are supported only on mips32r2, so I replaced this function with the
call to function cacheflush which works for both mips32r1 and mips32r2.
Patch by Sasa Stankovic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141564 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-10-10 18:41:02 +00:00
parent a86a58695d
commit 9d2fa87816
1 changed files with 5 additions and 34 deletions
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39
lib/Support/Memory.cpp
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@ -16,6 +16,10 @@
#include "llvm/Support/Valgrind.h"
#include "llvm/Config/config.h"
#if defined(__mips__)
#include <sys/cachectl.h>
#endif
namespace llvm {
using namespace sys;
}
@ -30,39 +34,6 @@ using namespace sys;
extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
/// ClearMipsCache - Invalidates instruction cache for Mips. This assembly code
/// is copied from the MIPS32 Instruction Set Reference. Since the code ends
/// with the return instruction "jr.hb ra" (Jump Register with Hazard Barrier),
/// it must be implemented as a function (which is called from the
/// InvalidateInstructionCache function). It cannot be directly inlined into
/// InvalidateInstructionCache function, because in that case the epilog of
/// InvalidateInstructionCache will not be executed.
#if defined(__mips__)
extern "C" void ClearMipsCache(const void* Addr, size_t Size);
asm volatile(
".text\n"
".align 2\n"
".globl ClearMipsCache\n"
"ClearMipsCache:\n"
".set noreorder\n"
"beq $a1, $zero, 20f\n" /* If size==0, branch around */
"nop\n"
"addu $a1, $a0, $a1\n" /* Calculate end address + 1 */
"rdhwr $v0, $1\n" /* Get step size for SYNCI */
/* $1 is $HW_SYNCI_Step */
"beq $v0, $zero, 20f\n" /* If no caches require synchronization, */
/* branch around */
"nop\n"
"10: synci 0($a0)\n" /* Synchronize all caches around address */
"sltu $v1, $a0, $a1\n" /* Compare current with end address */
"bne $v1, $zero, 10b\n" /* Branch if more to do */
"addu $a0, $a0, $v0\n" /* Add step size in delay slot */
"sync\n" /* Clear memory hazards */
"20: jr.hb $ra\n" /* Return, clearing instruction hazards */
"nop\n"
);
#endif
/// InvalidateInstructionCache - Before the JIT can run a block of code
/// that has been emitted it must invalidate the instruction cache on some
/// platforms.
@ -100,7 +71,7 @@ void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr,
char *End = Start + Len;
__clear_cache(Start, End);
# elif defined(__mips__)
ClearMipsCache(Addr, Len);
cacheflush((char*)Addr, Len, BCACHE);
# endif
#endif // end apple