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Fix some bugs in the alpha backend, some of which I introduced yesterday,

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and some that were preexisting.  All alpha regtests pass now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22829 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-08-17 17:08:24 +00:00
parent 491dfa88e4
commit 9d6c45bdd7
1 changed files with 3 additions and 2 deletions
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5
lib/Target/Alpha/AlphaISelPattern.cpp
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@@ -284,6 +284,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
case MVT::f32: case MVT::f32:
args_float[count] = AddLiveIn(MF,args_float[count], getRegClassFor(VT)); args_float[count] = AddLiveIn(MF,args_float[count], getRegClassFor(VT));
argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT); argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
DAG.setRoot(argt.getValue(1));
break; break;
case MVT::i1: case MVT::i1:
case MVT::i8: case MVT::i8:
@@ -292,12 +293,12 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
case MVT::i64: case MVT::i64:
args_int[count] = AddLiveIn(MF, args_int[count], args_int[count] = AddLiveIn(MF, args_int[count],
getRegClassFor(MVT::i64)); getRegClassFor(MVT::i64));
argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], VT); argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
DAG.setRoot(argt.getValue(1));
if (VT != MVT::i64) if (VT != MVT::i64)
argt = DAG.getNode(ISD::TRUNCATE, VT, argt); argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
break; break;
} }
DAG.setRoot(argt.getValue(1));
} else { //more args } else { //more args
// Create the frame index object for this incoming parameter... // Create the frame index object for this incoming parameter...
int FI = MFI->CreateFixedObject(8, 8 * (count - 6)); int FI = MFI->CreateFixedObject(8, 8 * (count - 6));