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Add alternative support for FP_ROUND from v2f32 to v2f64
- Due to the current matching vector elements constraints in ISD::FP_EXTEND, rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPEXT to work around this constraints. This patch also reverts a previous attempt to fix this issue by recovering the scalarized ISD::FP_EXTEND pattern and thus significantly reduces the overhead of supporting non-power-2 vector FP extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165625 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -634,7 +634,7 @@ private:
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SDValue WidenVecRes_InregOp(SDNode *N);
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// Widen Vector Operand.
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bool WidenVectorOperand(SDNode *N, unsigned ResNo);
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bool WidenVectorOperand(SDNode *N, unsigned OpNo);
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SDValue WidenVecOp_BITCAST(SDNode *N);
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SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
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SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
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@ -2082,16 +2082,20 @@ SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
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//===----------------------------------------------------------------------===//
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// Widen Vector Operand
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//===----------------------------------------------------------------------===//
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bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
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DEBUG(dbgs() << "Widen node operand " << ResNo << ": ";
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bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
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DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
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N->dump(&DAG);
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dbgs() << "\n");
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SDValue Res = SDValue();
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// See if the target wants to custom widen this node.
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if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
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return false;
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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dbgs() << "WidenVectorOperand op #" << ResNo << ": ";
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dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
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N->dump(&DAG);
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dbgs() << "\n";
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#endif
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@ -939,6 +939,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
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setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
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setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
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}
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@ -5161,86 +5163,6 @@ X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
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return SDValue();
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}
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// LowerVectorFpExtend - Recognize the scalarized FP_EXTEND from v2f32 to v2f64
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// and convert it into X86ISD::VFPEXT due to the current ISD::FP_EXTEND has the
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// constraint of matching input/output vector elements.
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SDValue
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X86TargetLowering::LowerVectorFpExtend(SDValue &Op, SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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SDNode *N = Op.getNode();
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EVT VT = Op.getValueType();
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unsigned NumElts = Op.getNumOperands();
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// Check supported types and sub-targets.
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//
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// Only v2f32 -> v2f64 needs special handling.
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if (VT != MVT::v2f64 || !Subtarget->hasSSE2())
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return SDValue();
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SDValue VecIn;
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EVT VecInVT;
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SmallVector<int, 8> Mask;
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EVT SrcVT = MVT::Other;
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// Check the patterns could be translated into X86vfpext.
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for (unsigned i = 0; i < NumElts; ++i) {
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SDValue In = N->getOperand(i);
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unsigned Opcode = In.getOpcode();
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// Skip if the element is undefined.
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if (Opcode == ISD::UNDEF) {
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Mask.push_back(-1);
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continue;
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}
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// Quit if one of the elements is not defined from 'fpext'.
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if (Opcode != ISD::FP_EXTEND)
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return SDValue();
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// Check how the source of 'fpext' is defined.
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SDValue L2In = In.getOperand(0);
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EVT L2InVT = L2In.getValueType();
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// Check the original type
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if (SrcVT == MVT::Other)
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SrcVT = L2InVT;
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else if (SrcVT != L2InVT) // Quit if non-homogenous typed.
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return SDValue();
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// Check whether the value being 'fpext'ed is extracted from the same
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// source.
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Opcode = L2In.getOpcode();
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// Quit if it's not extracted with a constant index.
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if (Opcode != ISD::EXTRACT_VECTOR_ELT ||
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!isa<ConstantSDNode>(L2In.getOperand(1)))
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return SDValue();
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SDValue ExtractedFromVec = L2In.getOperand(0);
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if (VecIn.getNode() == 0) {
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VecIn = ExtractedFromVec;
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VecInVT = ExtractedFromVec.getValueType();
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} else if (VecIn != ExtractedFromVec) // Quit if built from more than 1 vec.
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return SDValue();
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Mask.push_back(cast<ConstantSDNode>(L2In.getOperand(1))->getZExtValue());
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}
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// Quit if all operands of BUILD_VECTOR are undefined.
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if (!VecIn.getNode())
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return SDValue();
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// Fill the remaining mask as undef.
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for (unsigned i = NumElts; i < VecInVT.getVectorNumElements(); ++i)
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Mask.push_back(-1);
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return DAG.getNode(X86ISD::VFPEXT, DL, VT,
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DAG.getVectorShuffle(VecInVT, DL,
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VecIn, DAG.getUNDEF(VecInVT),
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&Mask[0]));
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}
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SDValue
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X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc dl = Op.getDebugLoc();
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@ -5273,10 +5195,6 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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if (Broadcast.getNode())
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return Broadcast;
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SDValue FpExt = LowerVectorFpExtend(Op, DAG);
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if (FpExt.getNode())
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return FpExt;
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unsigned EVTBits = ExtVT.getSizeInBits();
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unsigned NumZero = 0;
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@ -8215,6 +8133,20 @@ SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
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return FIST;
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}
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SDValue X86TargetLowering::lowerFP_EXTEND(SDValue Op,
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SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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SDValue In = Op.getOperand(0);
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EVT SVT = In.getValueType();
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assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
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return DAG.getNode(X86ISD::VFPEXT, DL, VT,
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DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
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In, DAG.getUNDEF(SVT)));
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}
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SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
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LLVMContext *Context = DAG.getContext();
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DebugLoc dl = Op.getDebugLoc();
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@ -11407,6 +11339,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
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case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
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case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
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case ISD::FP_EXTEND: return lowerFP_EXTEND(Op, DAG);
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case ISD::FABS: return LowerFABS(Op, DAG);
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case ISD::FNEG: return LowerFNEG(Op, DAG);
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case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
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@ -788,6 +788,7 @@ namespace llvm {
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SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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@ -818,8 +819,6 @@ namespace llvm {
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SDValue LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVectorFpExtend(SDValue &Op, SelectionDAG &DAG) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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