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Rewrite TargetMaterializeConstant splitting it out into two functions
for integer and fp constants. Implement todo to use vfp3 instructions to materialize easy constants if we can. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113453 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -124,6 +124,8 @@ class ARMFastISel : public FastISel {
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bool ARMLoadAlloca(const Instruction *I, EVT VT);
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bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
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bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
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unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
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unsigned ARMMaterializeInt(const Constant *C);
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bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
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const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
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@ -323,18 +325,40 @@ unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
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return ResultReg;
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}
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unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
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EVT VT = TLI.getValueType(C->getType(), true);
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// For double width floating point we need to materialize two constants
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// (the high and the low) into integer registers then use a move to get
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// the combined constant into an FP reg.
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unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
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const APFloat Val = CFP->getValueAPF();
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bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
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// Only handle simple types.
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if (!VT.isSimple()) return 0;
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// This checks to see if we can use VFP3 instructions to materialize
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// a constant, otherwise we have to go through the constant pool.
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if (TLI.isFPImmLegal(Val, VT)) {
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unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
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unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
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DestReg)
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.addFPImm(CFP));
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return DestReg;
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}
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// Handle double width floating point?
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if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
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// No 64-bit at the moment.
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if (is64bit) return 0;
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// TODO: Theoretically we could materialize fp constants directly with
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// instructions from VFP3.
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// Load this from the constant pool.
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unsigned DestReg = ARMMaterializeInt(cast<Constant>(CFP));
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// If we have a floating point constant we expect it in a floating point
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// register.
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unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::VMOVRS), MoveReg)
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.addReg(DestReg));
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return MoveReg;
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}
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unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
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// MachineConstantPool wants an explicit alignment.
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unsigned Align = TD.getPrefTypeAlignment(C->getType());
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if (Align == 0) {
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@ -354,20 +378,20 @@ unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
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.addReg(DestReg).addConstantPoolIndex(Idx)
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.addReg(0).addImm(0));
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// If we have a floating point constant we expect it in a floating point
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// register.
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// TODO: Make this use ARMBaseInstrInfo::copyPhysReg.
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if (C->getType()->isFloatTy()) {
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unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::VMOVRS), MoveReg)
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.addReg(DestReg));
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return MoveReg;
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}
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return DestReg;
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}
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unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
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EVT VT = TLI.getValueType(C->getType(), true);
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// Only handle simple types.
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if (!VT.isSimple()) return 0;
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if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return ARMMaterializeFP(CFP, VT);
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return ARMMaterializeInt(C);
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}
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bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
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VT = TLI.getValueType(Ty, true);
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