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A8.6.188 STC, STC2

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The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.

rdar://problem/9200661


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-29 19:49:38 +00:00
parent 4381dd1f21
commit 9eda569a74
2 changed files with 9 additions and 3 deletions
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6
lib/Target/ARM/ARMInstrInfo.td
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@ -3430,8 +3430,8 @@ multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
}
def _OPTION : ACI<(outs),
(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
opc, "\tp$cop, cr$CRd, [$base], $option"> {
(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
let Inst{31-28} = op31_28;
let Inst{24} = 0; // P = 0
let Inst{23} = 1; // U = 1
@ -3472,7 +3472,7 @@ multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
def L_OPTION : ACI<(outs),
(ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
!strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
!strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
let Inst{31-28} = op31_28;
let Inst{24} = 0; // P = 0
let Inst{23} = 1; // U = 1

6
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -202,3 +202,9 @@
# CHECK: pli [r3, r1, lsl #2]
0x01 0xf1 0xd3 0xf6
# CHECK: stc p2, cr4, [r9], {157}
0x9d 0x42 0x89 0xec
# CHECK: stc2 p2, cr4, [r9], {157}
0x9d 0x42 0x89 0xfc