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https://github.com/c64scene-ar/llvm-6502.git
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Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -88,7 +88,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
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assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
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"Extract subreg and Dst must be of same register class");
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MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC);
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MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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}
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@@ -157,7 +157,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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} else {
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TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
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}
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MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
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MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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@@ -184,7 +184,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
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"Insert superreg and Dst must be of same register class");
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MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0);
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MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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@@ -206,7 +206,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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} else {
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TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
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}
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MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
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MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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