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https://github.com/c64scene-ar/llvm-6502.git
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More soft-fp work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32559 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -488,9 +488,9 @@ void SelectionDAGLegalize::HandleOp(SDOperand Op) {
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}
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}
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/// ExpandConstantFP - Expands the ConstantFP node by either converting it to
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/// integer constant or spilling the constant to memory.
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static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool ToMem,
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/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
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/// a load from the constant pool.
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static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
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SelectionDAG &DAG, TargetLowering &TLI) {
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bool Extend = false;
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@ -502,7 +502,7 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool ToMem,
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bool isDouble = VT == MVT::f64;
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ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
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Type::FloatTy, CFP->getValue());
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if (!ToMem) {
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if (!UseCP) {
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double Val = LLVMC->getValue();
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return isDouble
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? DAG.getConstant(DoubleToBits(Val), MVT::i64)
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@ -4434,6 +4434,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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case ISD::ConstantFP: {
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ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
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Lo = ExpandConstantFP(CFP, false, DAG, TLI);
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if (getTypeAction(Lo.getValueType()) == Expand)
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ExpandOp(Lo, Lo, Hi);
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break;
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}
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case ISD::BUILD_PAIR:
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@ -4526,6 +4528,9 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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// f32->i32 or f64->i64 one to one expansion.
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// Remember that we legalized the chain.
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AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
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// Recursively expand the new load.
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if (getTypeAction(NVT) == Expand)
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ExpandOp(Lo, Lo, Hi);
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break;
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}
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@ -346,13 +346,10 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
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// If this value is represented with multiple target registers, make sure
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// to create enough consecutive registers of the right (smaller) type.
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unsigned NT = VT-1; // Find the type to use.
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while (TLI.getNumElements((MVT::ValueType)NT) != 1)
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--NT;
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unsigned R = MakeReg((MVT::ValueType)NT);
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VT = TLI.getTypeToExpandTo(VT);
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unsigned R = MakeReg(VT);
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for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
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MakeReg((MVT::ValueType)NT);
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MakeReg(VT);
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return R;
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}
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@ -689,19 +686,26 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
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// If this type is not legal, make it so now.
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if (VT != MVT::Vector) {
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MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
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N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
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if (DestVT < VT) {
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if (TLI.getTypeAction(VT) == TargetLowering::Expand) {
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// Source must be expanded. This input value is actually coming from the
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// register pair VMI->second and VMI->second+1.
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N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
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DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
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} else if (DestVT > VT) { // Promotion case
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if (MVT::isFloatingPoint(VT))
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N = DAG.getNode(ISD::FP_ROUND, VT, N);
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else
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N = DAG.getNode(ISD::TRUNCATE, VT, N);
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MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
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unsigned NumVals = TLI.getNumElements(VT);
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N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
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if (NumVals == 1)
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N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
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else {
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assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
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N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
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DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
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}
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} else {
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MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
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N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
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if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case
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N = MVT::isFloatingPoint(VT)
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? DAG.getNode(ISD::FP_ROUND, VT, N)
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: DAG.getNode(ISD::TRUNCATE, VT, N);
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}
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} else {
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// Otherwise, if this is a vector, make it available as a generic vector
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@ -2916,12 +2920,8 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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// If this is a large integer, it needs to be broken up into small
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// integers. Figure out what the destination type is and how many small
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// integers it turns into.
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MVT::ValueType NVT = VT;
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unsigned NumVals = 1;
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while (getTypeAction(NVT) == Expand) {
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NVT = getTypeToTransformTo(NVT);
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NumVals *= MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
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}
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MVT::ValueType NVT = getTypeToExpandTo(VT);
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unsigned NumVals = getNumElements(VT);
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for (unsigned i = 0; i != NumVals; ++i)
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RetVals.push_back(NVT);
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} else {
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@ -3131,12 +3131,8 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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// If this is a large integer, it needs to be reassembled from small
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// integers. Figure out what the source elt type is and how many small
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// integers it is.
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MVT::ValueType NVT = VT;
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unsigned NumVals = 1;
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while (getTypeAction(NVT) == Expand) {
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NVT = getTypeToTransformTo(NVT);
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NumVals *= MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
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}
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MVT::ValueType NVT = getTypeToExpandTo(VT);
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unsigned NumVals = getNumElements(VT);
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for (unsigned i = 0; i != NumVals; ++i)
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RetTys.push_back(NVT);
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} else {
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@ -3935,17 +3931,20 @@ SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
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}
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return DAG.getNode(ISD::TokenFactor, MVT::Other,
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&OutChains[0], OutChains.size());
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} else if (SrcVT < DestVT) {
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} else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) {
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// The src value is promoted to the register.
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if (MVT::isFloatingPoint(SrcVT))
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Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
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else
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Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
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return DAG.getCopyToReg(getRoot(), Reg, Op);
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} else if (SrcVT == MVT::f32 || SrcVT == MVT::f64) {
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return DAG.getCopyToReg(getRoot(), Reg,
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DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
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} else {
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DestVT = TLI.getTypeToExpandTo(SrcVT);
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unsigned NumVals = TLI.getNumElements(SrcVT);
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if (NumVals == 1)
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return DAG.getCopyToReg(getRoot(), Reg,
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DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
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assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
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// The src value is expanded into multiple registers.
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
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Op, DAG.getConstant(0, TLI.getPointerTy()));
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