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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Improve operand validation for Thumb2 addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
14605d1a67
commit
9fe72bcd37
@ -839,10 +839,11 @@ multiclass T2I_cmp_irs<bits<4> opcod, string opc,
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/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
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multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
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def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
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InstrItinClass iii, InstrItinClass iis, RegisterClass target,
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PatFrag opnode> {
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def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
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opc, ".w\t$Rt, $addr",
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[(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
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[(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-25} = 0b00;
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let Inst{24} = signed;
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@ -859,9 +860,9 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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let Inst{23} = addr{12}; // U
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let Inst{11-0} = addr{11-0}; // imm
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}
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def i8 : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
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def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_imm8:$addr), iii,
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opc, "\t$Rt, $addr",
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[(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
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[(set target:$Rt, (opnode t2addrmode_imm8:$addr))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-25} = 0b00;
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let Inst{24} = signed;
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@ -881,9 +882,9 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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let Inst{9} = addr{8}; // U
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let Inst{7-0} = addr{7-0}; // imm
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}
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def s : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
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def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
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opc, ".w\t$Rt, $addr",
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[(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
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[(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-25} = 0b00;
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let Inst{24} = signed;
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@ -904,9 +905,9 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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}
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// FIXME: Is the pci variant actually needed?
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def pci : T2Ipc <(outs GPR:$Rt), (ins t2ldrlabel:$addr), iii,
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def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
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opc, ".w\t$Rt, $addr",
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[(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
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[(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
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let isReMaterializable = 1;
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let Inst{31-27} = 0b11111;
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let Inst{26-25} = 0b00;
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@ -924,10 +925,11 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
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/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
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multiclass T2I_st<bits<2> opcod, string opc,
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InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
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def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
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InstrItinClass iii, InstrItinClass iis, RegisterClass target,
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PatFrag opnode> {
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def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
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opc, ".w\t$Rt, $addr",
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[(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
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[(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0001;
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let Inst{22-21} = opcod;
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@ -942,9 +944,9 @@ multiclass T2I_st<bits<2> opcod, string opc,
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let Inst{23} = addr{12}; // U
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let Inst{11-0} = addr{11-0}; // imm
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}
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def i8 : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
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def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_imm8:$addr), iii,
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opc, "\t$Rt, $addr",
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[(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
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[(opnode target:$Rt, t2addrmode_imm8:$addr)]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0000;
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let Inst{22-21} = opcod;
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@ -962,9 +964,9 @@ multiclass T2I_st<bits<2> opcod, string opc,
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let Inst{9} = addr{8}; // U
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let Inst{7-0} = addr{7-0}; // imm
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}
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def s : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
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def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
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opc, ".w\t$Rt, $addr",
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[(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
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[(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0000;
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let Inst{22-21} = opcod;
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@ -1118,20 +1120,20 @@ def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
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// Load
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
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defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
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UnOpFrag<(load node:$Src)>>;
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// Loads with zero extension
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defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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UnOpFrag<(zextloadi16 node:$Src)>>;
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rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
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defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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UnOpFrag<(zextloadi8 node:$Src)>>;
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rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
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// Loads with sign extension
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defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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UnOpFrag<(sextloadi16 node:$Src)>>;
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rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
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defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
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UnOpFrag<(sextloadi8 node:$Src)>>;
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rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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// Load doubleword
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@ -1274,12 +1276,12 @@ def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
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def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
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// Store
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defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
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defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
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BinOpFrag<(store node:$LHS, node:$RHS)>>;
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defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
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BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
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rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
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defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
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BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
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rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
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// Store doubleword
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
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@ -1288,53 +1290,53 @@ def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
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IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
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// Indexed stores
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def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPRnopc:$base_wb),
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(ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
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"str", "\t$Rt, [$Rn, $addr]!",
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"$Rn = $base_wb,@earlyclobber $base_wb",
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[(set GPR:$base_wb,
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(pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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[(set GPRnopc:$base_wb,
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(pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
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def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPRnopc:$base_wb),
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(ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
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"str", "\t$Rt, [$Rn], $addr",
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"$Rn = $base_wb,@earlyclobber $base_wb",
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[(set GPR:$base_wb,
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(post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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[(set GPRnopc:$base_wb,
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(post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
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def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPRnopc:$base_wb),
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(ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
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"strh", "\t$Rt, [$Rn, $addr]!",
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"$Rn = $base_wb,@earlyclobber $base_wb",
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[(set GPR:$base_wb,
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(pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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[(set GPRnopc:$base_wb,
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(pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
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def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPRnopc:$base_wb),
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(ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
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"strh", "\t$Rt, [$Rn], $addr",
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"$Rn = $base_wb,@earlyclobber $base_wb",
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[(set GPR:$base_wb,
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(post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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[(set GPRnopc:$base_wb,
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(post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
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def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPRnopc:$base_wb),
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(ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
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"strb", "\t$Rt, [$Rn, $addr]!",
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"$Rn = $base_wb,@earlyclobber $base_wb",
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[(set GPR:$base_wb,
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(pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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[(set GPRnopc:$base_wb,
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(pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
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def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
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(ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
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def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPRnopc:$base_wb),
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(ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
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AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
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"strb", "\t$Rt, [$Rn], $addr",
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"$Rn = $base_wb,@earlyclobber $base_wb",
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[(set GPR:$base_wb,
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(post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
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[(set GPRnopc:$base_wb,
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(post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
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// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
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// only.
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@ -1,11 +1,10 @@
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# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
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# XFAIL: *
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# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1|
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# -------------------------------------------------------------------------------------------------
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#
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#
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# if Rt = '1111' then SEE "Unallocated memory hints"
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0xb3 0xf9 0xdf 0xf8
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@ -1,11 +1,10 @@
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# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
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# XFAIL: *
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# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
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# -------------------------------------------------------------------------------------------------
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#
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#
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# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints"
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0x35 0xf9 0x00 0xfc
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@ -1,11 +1,10 @@
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# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
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# XFAIL: *
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# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25)
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1|
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# -------------------------------------------------------------------------------------------------
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#
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#
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# if Rn == '1111' then UNDEFINED
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0x4f 0xf8 0xff 0xeb
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