Print "dregpair" NEON operands with a space between them, for readability and

consistency with other instructions that have lists of register operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp

@@ -307,7 +307,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
       unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0);
       unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1);
       O << '{'
-        << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
+        << getRegisterName(DRegLo) << ", " << getRegisterName(DRegHi)
         << '}';
     } else if (Modifier && strcmp(Modifier, "lane") == 0) {
       unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);

test/CodeGen/ARM/reg_sequence.ll

@@ -240,8 +240,8 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
 ; CHECK:        vldr.64
 ; CHECK-NOT:    vmov d{{.*}}, d0
 ; CHECK:        vmov.i8 d1
-; CHECK-NEXT:   vstmia r0, {d0,d1}
-; CHECK-NEXT:   vstmia r0, {d0,d1}
+; CHECK-NEXT:   vstmia r0, {d0, d1}
+; CHECK-NEXT:   vstmia r0, {d0, d1}
   %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2]
   %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
   store <4 x float> %4, <4 x float>* undef, align 16

test/CodeGen/Thumb2/machine-licm.ll

@@ -56,7 +56,7 @@ define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
 entry:
 ; CHECK: t2:
 ; CHECK: adr r{{.}}, #LCPI1_0
-; CHECK: vldmia r3, {d0,d1}
+; CHECK: vldmia r3, {d0, d1}
   br i1 undef, label %bb1, label %bb2
 
 bb1: