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Cleanup: Delete seemingly unused reference to MachineDominatorTree from ScheduleDAGInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216124 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -107,9 +107,7 @@ protected:
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std::map<MachineInstr*, SUnit*> MIToSUnit;
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public:
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VLIWPacketizerList(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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bool IsPostRA);
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VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, bool IsPostRA);
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virtual ~VLIWPacketizerList();
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@ -250,7 +250,7 @@ protected:
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public:
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ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
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bool IsPostRA)
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: ScheduleDAGInstrs(*C->MF, C->MLI, C->MDT, IsPostRA,
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: ScheduleDAGInstrs(*C->MF, C->MLI, IsPostRA,
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/*RemoveKillFlags=*/IsPostRA, C->LIS),
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AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(),
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CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) {
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@ -76,7 +76,6 @@ namespace llvm {
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class ScheduleDAGInstrs : public ScheduleDAG {
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protected:
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const MachineLoopInfo *MLI;
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const MachineDominatorTree *MDT;
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const MachineFrameInfo *MFI;
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/// Live Intervals provides reaching defs in preRA scheduling.
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@ -155,7 +154,6 @@ namespace llvm {
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public:
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explicit ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo *mli,
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const MachineDominatorTree *mdt,
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bool IsPostRAFlag,
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bool RemoveKillFlags = false,
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LiveIntervals *LIS = nullptr);
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@ -106,16 +106,15 @@ namespace llvm {
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class DefaultVLIWScheduler : public ScheduleDAGInstrs {
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public:
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DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
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MachineDominatorTree &MDT, bool IsPostRA);
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bool IsPostRA);
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// Schedule - Actual scheduling work.
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void schedule() override;
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};
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}
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DefaultVLIWScheduler::DefaultVLIWScheduler(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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bool IsPostRA) :
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ScheduleDAGInstrs(MF, &MLI, &MDT, IsPostRA) {
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DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
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MachineLoopInfo &MLI, bool IsPostRA)
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: ScheduleDAGInstrs(MF, &MLI, IsPostRA) {
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CanHandleTerminators = true;
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}
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@ -125,12 +124,12 @@ void DefaultVLIWScheduler::schedule() {
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}
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// VLIWPacketizerList Ctor
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VLIWPacketizerList::VLIWPacketizerList(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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bool IsPostRA) : TM(MF.getTarget()), MF(MF) {
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VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF,
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MachineLoopInfo &MLI, bool IsPostRA)
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: TM(MF.getTarget()), MF(MF) {
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TII = TM.getSubtargetImpl()->getInstrInfo();
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ResourceTracker = TII->CreateTargetScheduleState(&TM, nullptr);
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VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
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VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, IsPostRA);
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}
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// VLIWPacketizerList Dtor
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@ -137,10 +137,10 @@ namespace {
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public:
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SchedulePostRATDList(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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AliasAnalysis *AA, const RegisterClassInfo&,
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TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
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SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs);
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MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA,
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const RegisterClassInfo &,
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TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
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SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs);
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~SchedulePostRATDList();
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@ -193,11 +193,11 @@ INITIALIZE_PASS(PostRAScheduler, "post-RA-sched",
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"Post RA top-down list latency scheduler", false, false)
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SchedulePostRATDList::SchedulePostRATDList(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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AliasAnalysis *AA, const RegisterClassInfo &RCI,
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TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
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SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs)
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: ScheduleDAGInstrs(MF, &MLI, &MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) {
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MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA,
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const RegisterClassInfo &RCI,
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TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
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SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs)
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: ScheduleDAGInstrs(MF, &MLI, /*IsPostRA=*/true), AA(AA), EndIndex(0) {
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const TargetMachine &TM = MF.getTarget();
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const InstrItineraryData *InstrItins =
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@ -269,7 +269,6 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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TII = Fn.getSubtarget().getInstrInfo();
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MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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AliasAnalysis *AA = &getAnalysis<AliasAnalysis>();
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TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
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@ -303,7 +302,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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DEBUG(dbgs() << "PostRAScheduler\n");
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SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
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SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
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CriticalPathRCs);
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// Loop over all of the basic blocks
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@ -51,11 +51,10 @@ static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo *mli,
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const MachineDominatorTree *mdt,
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bool IsPostRAFlag,
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bool RemoveKillFlags,
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LiveIntervals *lis)
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: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis),
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: ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(lis),
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IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags),
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CanHandleTerminators(false), FirstDbgValue(nullptr) {
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assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
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@ -118,7 +118,6 @@ namespace {
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public:
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// Ctor.
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HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
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MachineDominatorTree &MDT,
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const MachineBranchProbabilityInfo *MBPI);
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// initPacketizerState - initialize some internal flags.
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@ -184,20 +183,19 @@ INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
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// HexagonPacketizerList Ctor.
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HexagonPacketizerList::HexagonPacketizerList(
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MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT,
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const MachineBranchProbabilityInfo *MBPI)
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: VLIWPacketizerList(MF, MLI, MDT, true){
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MachineFunction &MF, MachineLoopInfo &MLI,
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const MachineBranchProbabilityInfo *MBPI)
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: VLIWPacketizerList(MF, MLI, true) {
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this->MBPI = MBPI;
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}
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bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
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const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
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MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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const MachineBranchProbabilityInfo *MBPI =
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&getAnalysis<MachineBranchProbabilityInfo>();
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// Instantiate the packetizer.
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HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI);
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HexagonPacketizerList Packetizer(Fn, MLI, MBPI);
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// DFA state table should not be empty.
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assert(Packetizer.getResourceTracker() && "Empty DFA table!");
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@ -148,9 +148,8 @@ private:
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}
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public:
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// Ctor.
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R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
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MachineDominatorTree &MDT)
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: VLIWPacketizerList(MF, MLI, MDT, true),
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R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI)
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: VLIWPacketizerList(MF, MLI, true),
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TII(static_cast<const R600InstrInfo *>(
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MF.getSubtarget().getInstrInfo())),
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TRI(TII->getRegisterInfo()) {
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@ -331,10 +330,9 @@ public:
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bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
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const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
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MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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// Instantiate the packetizer.
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R600PacketizerList Packetizer(Fn, MLI, MDT);
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R600PacketizerList Packetizer(Fn, MLI);
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// DFA state table should not be empty.
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assert(Packetizer.getResourceTracker() && "Empty DFA table!");
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