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Added soft fail cases for the disassembler when decoding MUL instructions on ARM.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga 2012-03-22 13:14:39 +00:00
parent e3295cc5be
commit a0c48eb8f6
2 changed files with 23 additions and 5 deletions
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11
lib/Target/ARM/ARMInstrInfo.td
View File

@ -3533,19 +3533,20 @@ class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
// property. Remove them when it's possible to add those properties
// on an individual MachineInstr, not just an instuction description.
let isCommutable = 1 in {
def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
[(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
Requires<[IsARM, HasV6]> {
let Inst{15-12} = 0b0000;
let Unpredictable{15-12} = 0b1111;
}
let Constraints = "@earlyclobber $Rd" in
def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
pred:$p, cc_out:$s),
4, IIC_iMUL32,
[(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
(MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
[(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
(MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
}

17
test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt Normal file
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@ -0,0 +1,17 @@
# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
# CHECK: potentially undefined
# CHECK: 0x93 0x12 0x01 0x00
0x93 0x12 0x01 0x00
# CHECK: potentially undefined
# CHECK: 0x92 0x0f 0x01 0x00
0x92 0x0f 0x01 0x00
# CHECK: potentially undefined
# CHECK: 0x9f 0x02 0x01 0x00
0x9f 0x02 0x01 0x00
# CHECK: potentially undefined
# CHECK: 0x92 0x01 0x0f 0x00
0x92 0x01 0x0f 0x00