mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-19 01:34:32 +00:00
Fixes to the X86 disassembler. The disassembler will now
return an error status in all failure cases, printing messages to debugs() only when debugging is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100229 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Callanan
parent
fd919200d4
commit
a144c3f34d
@ -21,8 +21,8 @@
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "X86GenRegisterNames.inc"
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@ -30,6 +30,14 @@
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using namespace llvm;
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using namespace llvm::X86Disassembler;
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void x86DisassemblerDebug(const char *file,
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unsigned line,
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const char *s) {
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dbgs() << file << ":" << line << ": " << s;
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}
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#define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
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namespace llvm {
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// Fill-ins to make the compiler happy. These constants are never actually
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@ -50,8 +58,8 @@ extern Target TheX86_32Target, TheX86_64Target;
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}
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static void translateInstruction(MCInst &target,
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InternalInstruction &source);
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static bool translateInstruction(MCInst &target,
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InternalInstruction &source);
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X86GenericDisassembler::X86GenericDisassembler(DisassemblerMode mode) :
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MCDisassembler(),
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@ -106,14 +114,13 @@ bool X86GenericDisassembler::getInstruction(MCInst &instr,
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address,
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fMode);
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if(ret) {
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if (ret) {
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size = internalInstr.readerCursor - address;
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return false;
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}
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else {
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size = internalInstr.length;
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translateInstruction(instr, internalInstr);
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return true;
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return !translateInstruction(instr, internalInstr);
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}
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}
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@ -151,29 +158,35 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate) {
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/// @param mcInst - The MCInst to append to.
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/// @param insn - The internal instruction to extract the R/M field
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/// from.
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static void translateRMRegister(MCInst &mcInst,
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/// @return - 0 on success; -1 otherwise
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static bool translateRMRegister(MCInst &mcInst,
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InternalInstruction &insn) {
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assert(insn.eaBase != EA_BASE_sib && insn.eaBase != EA_BASE_sib64 &&
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"A R/M register operand may not have a SIB byte");
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if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
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debug("A R/M register operand may not have a SIB byte");
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return true;
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}
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switch (insn.eaBase) {
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default:
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debug("Unexpected EA base register");
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return true;
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case EA_BASE_NONE:
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llvm_unreachable("EA_BASE_NONE for ModR/M base");
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break;
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debug("EA_BASE_NONE for ModR/M base");
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return true;
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#define ENTRY(x) case EA_BASE_##x:
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ALL_EA_BASES
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#undef ENTRY
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llvm_unreachable("A R/M register operand may not have a base; "
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"the operand must be a register.");
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break;
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#define ENTRY(x) \
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debug("A R/M register operand may not have a base; "
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"the operand must be a register.");
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return true;
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#define ENTRY(x) \
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case EA_REG_##x: \
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mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
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ALL_REGS
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#undef ENTRY
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default:
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llvm_unreachable("Unexpected EA base register");
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}
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return false;
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}
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/// translateRMMemory - Translates a memory operand stored in the Mod and R/M
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@ -186,7 +199,8 @@ static void translateRMRegister(MCInst &mcInst,
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/// @param sr - Whether or not to emit the segment register. The
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/// LEA instruction does not expect a segment-register
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/// operand.
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static void translateRMMemory(MCInst &mcInst,
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/// @return - 0 on success; nonzero otherwise
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static bool translateRMMemory(MCInst &mcInst,
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InternalInstruction &insn,
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bool sr) {
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// Addresses in an MCInst are represented as five operands:
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@ -211,7 +225,8 @@ static void translateRMMemory(MCInst &mcInst,
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if (insn.sibBase != SIB_BASE_NONE) {
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switch (insn.sibBase) {
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default:
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llvm_unreachable("Unexpected sibBase");
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debug("Unexpected sibBase");
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return true;
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#define ENTRY(x) \
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case SIB_BASE_##x: \
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baseReg = MCOperand::CreateReg(X86::x); break;
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@ -225,7 +240,8 @@ static void translateRMMemory(MCInst &mcInst,
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if (insn.sibIndex != SIB_INDEX_NONE) {
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switch (insn.sibIndex) {
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default:
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llvm_unreachable("Unexpected sibIndex");
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debug("Unexpected sibIndex");
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return true;
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#define ENTRY(x) \
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case SIB_INDEX_##x: \
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indexReg = MCOperand::CreateReg(X86::x); break;
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@ -241,9 +257,10 @@ static void translateRMMemory(MCInst &mcInst,
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} else {
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switch (insn.eaBase) {
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case EA_BASE_NONE:
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assert(insn.eaDisplacement != EA_DISP_NONE &&
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"EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
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if (insn.eaDisplacement == EA_DISP_NONE) {
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debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
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return true;
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}
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if (insn.mode == MODE_64BIT)
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baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
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else
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@ -271,8 +288,8 @@ static void translateRMMemory(MCInst &mcInst,
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indexReg = MCOperand::CreateReg(0);
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switch (insn.eaBase) {
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default:
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llvm_unreachable("Unexpected eaBase");
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break;
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debug("Unexpected eaBase");
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return true;
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// Here, we will use the fill-ins defined above. However,
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// BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
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// sib and sib64 were handled in the top-level if, so they're only
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@ -285,9 +302,9 @@ static void translateRMMemory(MCInst &mcInst,
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#define ENTRY(x) case EA_REG_##x:
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ALL_REGS
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#undef ENTRY
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llvm_unreachable("A R/M memory operand may not be a register; "
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"the base field must be a base.");
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break;
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debug("A R/M memory operand may not be a register; "
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"the base field must be a base.");
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return true;
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}
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}
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@ -315,6 +332,8 @@ static void translateRMMemory(MCInst &mcInst,
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if (sr)
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mcInst.addOperand(segmentReg);
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return false;
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}
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/// translateRM - Translates an operand stored in the R/M (and possibly SIB)
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@ -324,12 +343,14 @@ static void translateRMMemory(MCInst &mcInst,
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/// @param operand - The operand, as stored in the descriptor table.
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/// @param insn - The instruction to extract Mod, R/M, and SIB fields
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/// from.
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static void translateRM(MCInst &mcInst,
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OperandSpecifier &operand,
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InternalInstruction &insn) {
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/// @return - 0 on success; nonzero otherwise
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static bool translateRM(MCInst &mcInst,
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OperandSpecifier &operand,
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InternalInstruction &insn) {
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switch (operand.type) {
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default:
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llvm_unreachable("Unexpected type for a R/M operand");
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debug("Unexpected type for a R/M operand");
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return true;
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case TYPE_R8:
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case TYPE_R16:
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case TYPE_R32:
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@ -345,8 +366,7 @@ static void translateRM(MCInst &mcInst,
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case TYPE_DEBUGREG:
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case TYPE_CR32:
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case TYPE_CR64:
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translateRMRegister(mcInst, insn);
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break;
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return translateRMRegister(mcInst, insn);
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case TYPE_M:
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case TYPE_M8:
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case TYPE_M16:
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@ -364,11 +384,9 @@ static void translateRM(MCInst &mcInst,
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case TYPE_M1616:
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case TYPE_M1632:
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case TYPE_M1664:
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translateRMMemory(mcInst, insn, true);
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break;
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return translateRMMemory(mcInst, insn, true);
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case TYPE_LEA:
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translateRMMemory(mcInst, insn, false);
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break;
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return translateRMMemory(mcInst, insn, false);
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}
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}
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@ -377,11 +395,17 @@ static void translateRM(MCInst &mcInst,
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///
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/// @param mcInst - The MCInst to append to.
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/// @param stackPos - The stack position to translate.
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static void translateFPRegister(MCInst &mcInst,
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uint8_t stackPos) {
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assert(stackPos < 8 && "Invalid FP stack position");
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/// @return - 0 on success; nonzero otherwise.
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static bool translateFPRegister(MCInst &mcInst,
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uint8_t stackPos) {
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if (stackPos >= 8) {
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debug("Invalid FP stack position");
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return true;
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}
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mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
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return false;
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}
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/// translateOperand - Translates an operand stored in an internal instruction
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@ -390,25 +414,27 @@ static void translateFPRegister(MCInst &mcInst,
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/// @param mcInst - The MCInst to append to.
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/// @param operand - The operand, as stored in the descriptor table.
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/// @param insn - The internal instruction.
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static void translateOperand(MCInst &mcInst,
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OperandSpecifier &operand,
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InternalInstruction &insn) {
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/// @return - false on success; true otherwise.
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static bool translateOperand(MCInst &mcInst,
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OperandSpecifier &operand,
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InternalInstruction &insn) {
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switch (operand.encoding) {
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default:
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llvm_unreachable("Unhandled operand encoding during translation");
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debug("Unhandled operand encoding during translation");
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return true;
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case ENCODING_REG:
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translateRegister(mcInst, insn.reg);
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break;
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return false;
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case ENCODING_RM:
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translateRM(mcInst, operand, insn);
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break;
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return translateRM(mcInst, operand, insn);
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case ENCODING_CB:
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case ENCODING_CW:
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case ENCODING_CD:
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case ENCODING_CP:
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case ENCODING_CO:
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case ENCODING_CT:
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llvm_unreachable("Translation of code offsets isn't supported.");
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debug("Translation of code offsets isn't supported.");
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return true;
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case ENCODING_IB:
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case ENCODING_IW:
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case ENCODING_ID:
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@ -417,24 +443,22 @@ static void translateOperand(MCInst &mcInst,
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case ENCODING_Ia:
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translateImmediate(mcInst,
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insn.immediates[insn.numImmediatesTranslated++]);
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break;
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return false;
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case ENCODING_RB:
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case ENCODING_RW:
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case ENCODING_RD:
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case ENCODING_RO:
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translateRegister(mcInst, insn.opcodeRegister);
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break;
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return false;
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case ENCODING_I:
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translateFPRegister(mcInst, insn.opcodeModifier);
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break;
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return translateFPRegister(mcInst, insn.opcodeModifier);
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case ENCODING_Rv:
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translateRegister(mcInst, insn.opcodeRegister);
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break;
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return false;
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case ENCODING_DUP:
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translateOperand(mcInst,
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insn.spec->operands[operand.type - TYPE_DUP0],
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insn);
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break;
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return translateOperand(mcInst,
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insn.spec->operands[operand.type - TYPE_DUP0],
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insn);
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}
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}
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@ -443,9 +467,13 @@ static void translateOperand(MCInst &mcInst,
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///
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/// @param mcInst - The MCInst to populate with the instruction's data.
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/// @param insn - The internal instruction.
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static void translateInstruction(MCInst &mcInst,
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InternalInstruction &insn) {
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assert(insn.spec);
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/// @return - false on success; true otherwise.
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static bool translateInstruction(MCInst &mcInst,
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InternalInstruction &insn) {
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if (!insn.spec) {
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debug("Instruction has no specification");
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return true;
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}
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mcInst.setOpcode(insn.instructionID);
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@ -454,9 +482,14 @@ static void translateInstruction(MCInst &mcInst,
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insn.numImmediatesTranslated = 0;
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for (index = 0; index < X86_MAX_OPERANDS; ++index) {
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if (insn.spec->operands[index].encoding != ENCODING_NONE)
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translateOperand(mcInst, insn.spec->operands[index], insn);
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if (insn.spec->operands[index].encoding != ENCODING_NONE) {
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if (translateOperand(mcInst, insn.spec->operands[index], insn)) {
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return true;
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}
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}
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}
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return false;
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}
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static MCDisassembler *createX86_32Disassembler(const Target &T) {
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@ -13,7 +13,6 @@
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*
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*===----------------------------------------------------------------------===*/
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#include <assert.h> /* for assert() */
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#include <stdarg.h> /* for va_*() */
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#include <stdio.h> /* for vsnprintf() */
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#include <stdlib.h> /* for exit() */
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@ -26,17 +25,20 @@
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#define TRUE 1
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#define FALSE 0
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typedef int8_t bool;
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#ifdef __GNUC__
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#define NORETURN __attribute__((noreturn))
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#else
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#define NORETURN
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#endif
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#define unreachable(s) \
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do { \
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fprintf(stderr, "%s:%d: %s\n", __FILE__, __LINE__, s); \
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exit(-1); \
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} while (0);
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#ifndef NDEBUG
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#define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0)
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#else
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#define debug(s) do { } while (0)
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#endif
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/*
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* contextForAttrs - Client for the instruction context table. Takes a set of
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@ -84,7 +86,6 @@ static int modRMRequired(OpcodeType type,
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return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
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modrm_type != MODRM_ONEENTRY;
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unreachable("Unknown opcode type");
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return 0;
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}
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@ -96,16 +97,18 @@ static int modRMRequired(OpcodeType type,
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* @param insnContext - See modRMRequired().
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* @param opcode - See modRMRequired().
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* @param modRM - The ModR/M byte if required, or any value if not.
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* @return - The UID of the instruction, or 0 on failure.
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*/
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static InstrUID decode(OpcodeType type,
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InstructionContext insnContext,
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uint8_t opcode,
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uint8_t modRM) {
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InstructionContext insnContext,
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uint8_t opcode,
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uint8_t modRM) {
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struct ModRMDecision* dec;
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switch (type) {
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default:
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unreachable("Unknown opcode type");
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debug("Unknown opcode type");
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return 0;
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case ONEBYTE:
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dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
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break;
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@ -122,7 +125,8 @@ static InstrUID decode(OpcodeType type,
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switch (dec->modrm_type) {
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default:
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unreachable("Corrupt table! Unknown modrm_type");
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debug("Corrupt table! Unknown modrm_type");
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return 0;
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case MODRM_ONEENTRY:
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return dec->instructionIDs[0];
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case MODRM_SPLITRM:
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@ -133,8 +137,6 @@ static InstrUID decode(OpcodeType type,
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case MODRM_FULL:
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return dec->instructionIDs[modRM];
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}
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return 0;
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}
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/*
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@ -342,7 +344,8 @@ static int readPrefixes(struct InternalInstruction* insn) {
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insn->segmentOverride = SEG_OVERRIDE_GS;
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break;
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default:
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unreachable("Unhandled override");
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debug("Unhandled override");
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return -1;
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}
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if (prefixGroups[1])
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dbgprintf(insn, "Redundant Group 2 prefix");
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@ -376,7 +379,7 @@ static int readPrefixes(struct InternalInstruction* insn) {
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if ((byte & 0xf0) == 0x40) {
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uint8_t opcodeByte;
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if(lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
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if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
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dbgprintf(insn, "Redundant REX prefix");
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return -1;
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}
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@ -540,17 +543,17 @@ static int getIDWithAttrMask(uint16_t* instructionID,
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static BOOL is16BitEquvalent(const char* orig, const char* equiv) {
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off_t i;
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for(i = 0;; i++) {
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if(orig[i] == '\0' && equiv[i] == '\0')
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for (i = 0;; i++) {
|
||||
if (orig[i] == '\0' && equiv[i] == '\0')
|
||||
return TRUE;
|
||||
if(orig[i] == '\0' || equiv[i] == '\0')
|
||||
if (orig[i] == '\0' || equiv[i] == '\0')
|
||||
return FALSE;
|
||||
if(orig[i] != equiv[i]) {
|
||||
if((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
|
||||
if (orig[i] != equiv[i]) {
|
||||
if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
|
||||
continue;
|
||||
if((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
|
||||
if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
|
||||
continue;
|
||||
if((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
|
||||
if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
|
||||
continue;
|
||||
return FALSE;
|
||||
}
|
||||
@ -567,17 +570,17 @@ static BOOL is16BitEquvalent(const char* orig, const char* equiv) {
|
||||
static BOOL is64BitEquivalent(const char* orig, const char* equiv) {
|
||||
off_t i;
|
||||
|
||||
for(i = 0;; i++) {
|
||||
if(orig[i] == '\0' && equiv[i] == '\0')
|
||||
for (i = 0;; i++) {
|
||||
if (orig[i] == '\0' && equiv[i] == '\0')
|
||||
return TRUE;
|
||||
if(orig[i] == '\0' || equiv[i] == '\0')
|
||||
if (orig[i] == '\0' || equiv[i] == '\0')
|
||||
return FALSE;
|
||||
if(orig[i] != equiv[i]) {
|
||||
if((orig[i] == 'W' || orig[i] == 'L') && equiv[i] == 'Q')
|
||||
if (orig[i] != equiv[i]) {
|
||||
if ((orig[i] == 'W' || orig[i] == 'L') && equiv[i] == 'Q')
|
||||
continue;
|
||||
if((orig[i] == '1' || orig[i] == '3') && equiv[i] == '6')
|
||||
if ((orig[i] == '1' || orig[i] == '3') && equiv[i] == '6')
|
||||
continue;
|
||||
if((orig[i] == '6' || orig[i] == '2') && equiv[i] == '4')
|
||||
if ((orig[i] == '6' || orig[i] == '2') && equiv[i] == '4')
|
||||
continue;
|
||||
return FALSE;
|
||||
}
|
||||
@ -615,7 +618,7 @@ static int getID(struct InternalInstruction* insn) {
|
||||
else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
|
||||
attrMask |= ATTR_XD;
|
||||
|
||||
if(getIDWithAttrMask(&instructionID, insn, attrMask))
|
||||
if (getIDWithAttrMask(&instructionID, insn, attrMask))
|
||||
return -1;
|
||||
|
||||
/* The following clauses compensate for limitations of the tables. */
|
||||
@ -792,7 +795,8 @@ static int readSIB(struct InternalInstruction* insn) {
|
||||
SIB_BASE_EBP : SIB_BASE_RBP);
|
||||
break;
|
||||
case 0x3:
|
||||
unreachable("Cannot have Mod = 0b11 and a SIB byte");
|
||||
debug("Cannot have Mod = 0b11 and a SIB byte");
|
||||
return -1;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@ -903,7 +907,7 @@ static int readModRM(struct InternalInstruction* insn) {
|
||||
if (rm == 0x6) {
|
||||
insn->eaBase = EA_BASE_NONE;
|
||||
insn->eaDisplacement = EA_DISP_16;
|
||||
if(readDisplacement(insn))
|
||||
if (readDisplacement(insn))
|
||||
return -1;
|
||||
} else {
|
||||
insn->eaBase = (EABase)(insn->eaBaseBase + rm);
|
||||
@ -913,18 +917,18 @@ static int readModRM(struct InternalInstruction* insn) {
|
||||
case 0x1:
|
||||
insn->eaBase = (EABase)(insn->eaBaseBase + rm);
|
||||
insn->eaDisplacement = EA_DISP_8;
|
||||
if(readDisplacement(insn))
|
||||
if (readDisplacement(insn))
|
||||
return -1;
|
||||
break;
|
||||
case 0x2:
|
||||
insn->eaBase = (EABase)(insn->eaBaseBase + rm);
|
||||
insn->eaDisplacement = EA_DISP_16;
|
||||
if(readDisplacement(insn))
|
||||
if (readDisplacement(insn))
|
||||
return -1;
|
||||
break;
|
||||
case 0x3:
|
||||
insn->eaBase = (EABase)(insn->eaRegBase + rm);
|
||||
if(readDisplacement(insn))
|
||||
if (readDisplacement(insn))
|
||||
return -1;
|
||||
break;
|
||||
}
|
||||
@ -942,13 +946,13 @@ static int readModRM(struct InternalInstruction* insn) {
|
||||
insn->eaBase = (insn->addressSize == 4 ?
|
||||
EA_BASE_sib : EA_BASE_sib64);
|
||||
readSIB(insn);
|
||||
if(readDisplacement(insn))
|
||||
if (readDisplacement(insn))
|
||||
return -1;
|
||||
break;
|
||||
case 0x5:
|
||||
insn->eaBase = EA_BASE_NONE;
|
||||
insn->eaDisplacement = EA_DISP_32;
|
||||
if(readDisplacement(insn))
|
||||
if (readDisplacement(insn))
|
||||
return -1;
|
||||
break;
|
||||
default:
|
||||
@ -964,12 +968,12 @@ static int readModRM(struct InternalInstruction* insn) {
|
||||
case 0xc: /* in case REXW.b is set */
|
||||
insn->eaBase = EA_BASE_sib;
|
||||
readSIB(insn);
|
||||
if(readDisplacement(insn))
|
||||
if (readDisplacement(insn))
|
||||
return -1;
|
||||
break;
|
||||
default:
|
||||
insn->eaBase = (EABase)(insn->eaBaseBase + rm);
|
||||
if(readDisplacement(insn))
|
||||
if (readDisplacement(insn))
|
||||
return -1;
|
||||
break;
|
||||
}
|
||||
@ -993,11 +997,13 @@ static int readModRM(struct InternalInstruction* insn) {
|
||||
*valid = 1; \
|
||||
switch (type) { \
|
||||
default: \
|
||||
unreachable("Unhandled register type"); \
|
||||
debug("Unhandled register type"); \
|
||||
*valid = 0; \
|
||||
return 0; \
|
||||
case TYPE_Rv: \
|
||||
return base + index; \
|
||||
case TYPE_R8: \
|
||||
if(insn->rexPrefix && \
|
||||
if (insn->rexPrefix && \
|
||||
index >= 4 && index <= 7) { \
|
||||
return prefix##_SPL + (index - 4); \
|
||||
} else { \
|
||||
@ -1017,23 +1023,23 @@ static int readModRM(struct InternalInstruction* insn) {
|
||||
case TYPE_MM64: \
|
||||
case TYPE_MM32: \
|
||||
case TYPE_MM: \
|
||||
if(index > 7) \
|
||||
if (index > 7) \
|
||||
*valid = 0; \
|
||||
return prefix##_MM0 + index; \
|
||||
case TYPE_SEGMENTREG: \
|
||||
if(index > 5) \
|
||||
if (index > 5) \
|
||||
*valid = 0; \
|
||||
return prefix##_ES + index; \
|
||||
case TYPE_DEBUGREG: \
|
||||
if(index > 7) \
|
||||
if (index > 7) \
|
||||
*valid = 0; \
|
||||
return prefix##_DR0 + index; \
|
||||
case TYPE_CR32: \
|
||||
if(index > 7) \
|
||||
if (index > 7) \
|
||||
*valid = 0; \
|
||||
return prefix##_ECR0 + index; \
|
||||
case TYPE_CR64: \
|
||||
if(index > 8) \
|
||||
if (index > 8) \
|
||||
*valid = 0; \
|
||||
return prefix##_RCR0 + index; \
|
||||
} \
|
||||
@ -1050,6 +1056,7 @@ static int readModRM(struct InternalInstruction* insn) {
|
||||
* @param index - The existing value of the field as reported by readModRM().
|
||||
* @param valid - The address of a uint8_t. The target is set to 1 if the
|
||||
* field is valid for the register class; 0 if not.
|
||||
* @return - The proper value.
|
||||
*/
|
||||
GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
|
||||
GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
|
||||
@ -1071,7 +1078,8 @@ static int fixupReg(struct InternalInstruction *insn,
|
||||
|
||||
switch ((OperandEncoding)op->encoding) {
|
||||
default:
|
||||
unreachable("Expected a REG or R/M encoding in fixupReg");
|
||||
debug("Expected a REG or R/M encoding in fixupReg");
|
||||
return -1;
|
||||
case ENCODING_REG:
|
||||
insn->reg = (Reg)fixupRegValue(insn,
|
||||
(OperandType)op->type,
|
||||
@ -1102,26 +1110,29 @@ static int fixupReg(struct InternalInstruction *insn,
|
||||
* @param insn - The instruction whose opcode field is to be read.
|
||||
* @param inModRM - Indicates that the opcode field is to be read from the
|
||||
* ModR/M extension; useful for escape opcodes
|
||||
* @return - 0 on success; nonzero otherwise.
|
||||
*/
|
||||
static void readOpcodeModifier(struct InternalInstruction* insn) {
|
||||
static int readOpcodeModifier(struct InternalInstruction* insn) {
|
||||
dbgprintf(insn, "readOpcodeModifier()");
|
||||
|
||||
if (insn->consumedOpcodeModifier)
|
||||
return;
|
||||
return 0;
|
||||
|
||||
insn->consumedOpcodeModifier = TRUE;
|
||||
|
||||
switch(insn->spec->modifierType) {
|
||||
switch (insn->spec->modifierType) {
|
||||
default:
|
||||
unreachable("Unknown modifier type.");
|
||||
debug("Unknown modifier type.");
|
||||
return -1;
|
||||
case MODIFIER_NONE:
|
||||
unreachable("No modifier but an operand expects one.");
|
||||
debug("No modifier but an operand expects one.");
|
||||
return -1;
|
||||
case MODIFIER_OPCODE:
|
||||
insn->opcodeModifier = insn->opcode - insn->spec->modifierBase;
|
||||
break;
|
||||
return 0;
|
||||
case MODIFIER_MODRM:
|
||||
insn->opcodeModifier = insn->modRM - insn->spec->modifierBase;
|
||||
break;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1134,11 +1145,13 @@ static void readOpcodeModifier(struct InternalInstruction* insn) {
|
||||
* @param size - The width (in bytes) of the register being specified.
|
||||
* 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
|
||||
* RAX.
|
||||
* @return - 0 on success; nonzero otherwise.
|
||||
*/
|
||||
static void readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
|
||||
static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
|
||||
dbgprintf(insn, "readOpcodeRegister()");
|
||||
|
||||
readOpcodeModifier(insn);
|
||||
if (readOpcodeModifier(insn))
|
||||
return -1;
|
||||
|
||||
if (size == 0)
|
||||
size = insn->registerSize;
|
||||
@ -1147,9 +1160,9 @@ static void readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
|
||||
case 1:
|
||||
insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
|
||||
| insn->opcodeModifier));
|
||||
if(insn->rexPrefix &&
|
||||
insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
|
||||
insn->opcodeRegister < MODRM_REG_AL + 0x8) {
|
||||
if (insn->rexPrefix &&
|
||||
insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
|
||||
insn->opcodeRegister < MODRM_REG_AL + 0x8) {
|
||||
insn->opcodeRegister = (Reg)(MODRM_REG_SPL
|
||||
+ (insn->opcodeRegister - MODRM_REG_AL - 4));
|
||||
}
|
||||
@ -1161,7 +1174,7 @@ static void readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
|
||||
| insn->opcodeModifier));
|
||||
break;
|
||||
case 4:
|
||||
insn->opcodeRegister = (Reg)(MODRM_REG_EAX +
|
||||
insn->opcodeRegister = (Reg)(MODRM_REG_EAX
|
||||
+ ((bFromREX(insn->rexPrefix) << 3)
|
||||
| insn->opcodeModifier));
|
||||
break;
|
||||
@ -1171,6 +1184,8 @@ static void readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
|
||||
| insn->opcodeModifier));
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1190,8 +1205,10 @@ static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
|
||||
|
||||
dbgprintf(insn, "readImmediate()");
|
||||
|
||||
if (insn->numImmediatesConsumed == 2)
|
||||
unreachable("Already consumed two immediates");
|
||||
if (insn->numImmediatesConsumed == 2) {
|
||||
debug("Already consumed two immediates");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (size == 0)
|
||||
size = insn->immediateSize;
|
||||
@ -1274,29 +1291,35 @@ static int readOperands(struct InternalInstruction* insn) {
|
||||
return -1;
|
||||
break;
|
||||
case ENCODING_Iv:
|
||||
readImmediate(insn, insn->immediateSize);
|
||||
break;
|
||||
if (readImmediate(insn, insn->immediateSize))
|
||||
return -1;
|
||||
case ENCODING_Ia:
|
||||
readImmediate(insn, insn->addressSize);
|
||||
if (readImmediate(insn, insn->addressSize))
|
||||
return -1;
|
||||
break;
|
||||
case ENCODING_RB:
|
||||
readOpcodeRegister(insn, 1);
|
||||
if (readOpcodeRegister(insn, 1))
|
||||
return -1;
|
||||
break;
|
||||
case ENCODING_RW:
|
||||
readOpcodeRegister(insn, 2);
|
||||
if (readOpcodeRegister(insn, 2))
|
||||
return -1;
|
||||
break;
|
||||
case ENCODING_RD:
|
||||
readOpcodeRegister(insn, 4);
|
||||
if (readOpcodeRegister(insn, 4))
|
||||
return -1;
|
||||
break;
|
||||
case ENCODING_RO:
|
||||
readOpcodeRegister(insn, 8);
|
||||
if (readOpcodeRegister(insn, 8))
|
||||
return -1;
|
||||
break;
|
||||
case ENCODING_Rv:
|
||||
readOpcodeRegister(insn, 0);
|
||||
if (readOpcodeRegister(insn, 0))
|
||||
return -1;
|
||||
break;
|
||||
case ENCODING_I:
|
||||
readOpcodeModifier(insn);
|
||||
break;
|
||||
if (readOpcodeModifier(insn))
|
||||
return -1;
|
||||
case ENCODING_DUP:
|
||||
break;
|
||||
default:
|
||||
|
||||
@ -508,6 +508,17 @@ int decodeInstruction(struct InternalInstruction* insn,
|
||||
uint64_t startLoc,
|
||||
DisassemblerMode mode);
|
||||
|
||||
/* x86DisassemblerDebug - C-accessible function for printing a message to
|
||||
* debugs()
|
||||
* @param file - The name of the file printing the debug message.
|
||||
* @param line - The line number that printed the debug message.
|
||||
* @param s - The message to print.
|
||||
*/
|
||||
|
||||
void x86DisassemblerDebug(const char *file,
|
||||
unsigned line,
|
||||
const char *s);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user