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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-12 13:30:51 +00:00
[AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement
missing patterns for them.
Add a SIMD test subdirectory to hold tests for SIMD instruction
selection correctness and quality.
'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Greene
parent
31c488c8bd
commit
a20244d1ba
@ -165,12 +165,25 @@ void DecodeUNPCKLPDMask(unsigned NElts,
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/// datatypes and vector widths.
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void DecodeUNPCKLPMask(EVT VT,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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unsigned NumElts = VT.getVectorNumElements();
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unsigned NElts = VT.getVectorNumElements();
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// Handle vector lengths > 128 bits. Define a "section" as a set of
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// 128 bits. AVX defines UNPCK* to operate independently on 128-bit
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// sections.
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unsigned NumSections = VT.getSizeInBits() / 128;
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if (NumSections == 0 ) NumSections = 1; // Handle MMX
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unsigned NumSectionElts = NumElts / NumSections;
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for (unsigned i = 0; i != NElts/2; ++i) {
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ShuffleMask.push_back(i); // Reads from dest
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ShuffleMask.push_back(i+NElts); // Reads from src
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unsigned Start = 0;
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unsigned End = NumSectionElts / 2;
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for (unsigned s = 0; s < NumSections; ++s) {
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for (unsigned i = Start; i != End; ++i) {
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ShuffleMask.push_back(i); // Reads from dest/src1
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ShuffleMask.push_back(i+NumSectionElts); // Reads from src/src2
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}
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// Process the next 128 bits.
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Start += NumSectionElts;
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End += NumSectionElts;
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}
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}
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@ -3173,7 +3173,8 @@ bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
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bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
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unsigned NumElems = N->getValueType(0).getVectorNumElements();
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if (NumElems != 2 && NumElems != 4)
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if ((NumElems != 2 && NumElems != 4)
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|| N->getValueType(0).getSizeInBits() > 128)
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return false;
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for (unsigned i = 0; i < NumElems/2; ++i)
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@ -3195,19 +3196,36 @@ static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
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if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
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return false;
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for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
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int BitI = Mask[i];
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int BitI1 = Mask[i+1];
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if (!isUndefOrEqual(BitI, j))
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return false;
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if (V2IsSplat) {
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if (!isUndefOrEqual(BitI1, NumElts))
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return false;
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} else {
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if (!isUndefOrEqual(BitI1, j + NumElts))
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// Handle vector lengths > 128 bits. Define a "section" as a set of
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// 128 bits. AVX defines UNPCK* to operate independently on 128-bit
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// sections.
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unsigned NumSections = VT.getSizeInBits() / 128;
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if (NumSections == 0 ) NumSections = 1; // Handle MMX
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unsigned NumSectionElts = NumElts / NumSections;
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unsigned Start = 0;
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unsigned End = NumSectionElts;
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for (unsigned s = 0; s < NumSections; ++s) {
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for (unsigned i = Start, j = s * NumSectionElts;
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i != End;
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i += 2, ++j) {
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int BitI = Mask[i];
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int BitI1 = Mask[i+1];
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if (!isUndefOrEqual(BitI, j))
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return false;
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if (V2IsSplat) {
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if (!isUndefOrEqual(BitI1, NumElts))
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return false;
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} else {
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if (!isUndefOrEqual(BitI1, j + NumElts))
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return false;
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}
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}
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// Process the next 128 bits.
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Start += NumSectionElts;
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End += NumSectionElts;
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}
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return true;
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}
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@ -3255,14 +3273,27 @@ static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
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if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
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return false;
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for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
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int BitI = Mask[i];
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int BitI1 = Mask[i+1];
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if (!isUndefOrEqual(BitI, j))
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return false;
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if (!isUndefOrEqual(BitI1, j))
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return false;
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// Handle vector lengths > 128 bits. Define a "section" as a set of
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// 128 bits. AVX defines UNPCK* to operate independently on 128-bit
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// sections.
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unsigned NumSections = VT.getSizeInBits() / 128;
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if (NumSections == 0 ) NumSections = 1; // Handle MMX
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unsigned NumSectionElts = NumElems / NumSections;
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for (unsigned s = 0; s < NumSections; ++s) {
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for (unsigned i = s * NumSectionElts, j = s * NumSectionElts;
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i != NumSectionElts * (s + 1);
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i += 2, ++j) {
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int BitI = Mask[i];
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int BitI1 = Mask[i+1];
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if (!isUndefOrEqual(BitI, j))
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return false;
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if (!isUndefOrEqual(BitI1, j))
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return false;
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}
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}
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return true;
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}
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@ -132,6 +132,8 @@ def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
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def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>;
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def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>;
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def X86Unpcklpsy : SDNode<"X86ISD::VUNPCKLPSY", SDTShuff2Op>;
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def X86Unpcklpdy : SDNode<"X86ISD::VUNPCKLPDY", SDTShuff2Op>;
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def X86Unpckhps : SDNode<"X86ISD::UNPCKHPS", SDTShuff2Op>;
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def X86Unpckhpd : SDNode<"X86ISD::UNPCKHPD", SDTShuff2Op>;
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@ -5622,11 +5622,15 @@ def : Pat<(X86Movddup (bc_v2f64
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// Shuffle with UNPCKLPS
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
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(VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
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(VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
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(UNPCKLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
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(VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
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(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
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(UNPCKLPSrr VR128:$src1, VR128:$src2)>;
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@ -5644,11 +5648,15 @@ def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
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// Shuffle with UNPCKLPD
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
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(VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
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(VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
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(UNPCKLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
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(VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
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(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
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(UNPCKLPDrr VR128:$src1, VR128:$src2)>;
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5
test/CodeGen/X86/SIMD/dg.exp
Normal file
5
test/CodeGen/X86/SIMD/dg.exp
Normal file
@ -0,0 +1,5 @@
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load_lib llvm.exp
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if { [llvm_supports_target X86] } {
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RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
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}
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20
test/CodeGen/X86/SIMD/notvunpcklpd.ll
Normal file
20
test/CodeGen/X86/SIMD/notvunpcklpd.ll
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@ -0,0 +1,20 @@
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; RUN: llc < %s -mattr=+avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @try_([2 x <4 x double>]* noalias %incarray, [2 x <4 x double>]* noalias %incarrayb ) {
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entry:
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%incarray1 = alloca [2 x <4 x double>]*, align 8
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%incarrayb1 = alloca [2 x <4 x double>]*, align 8
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%carray = alloca [2 x <4 x double>], align 16
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%r = getelementptr [2 x <4 x double>]* %incarray, i32 0, i32 0
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%rb = getelementptr [2 x <4 x double>]* %incarrayb, i32 0, i32 0
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%r3 = load <4 x double>* %r, align 8
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%r4 = load <4 x double>* %rb, align 8
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%r11 = shufflevector <4 x double> %r3, <4 x double> %r4, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x double>> [#uses=1]
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; CHECK-NOT: vunpcklpd
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%r12 = getelementptr [2 x <4 x double>]* %carray, i32 0, i32 1
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store <4 x double> %r11, <4 x double>* %r12, align 4
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ret void
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}
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20
test/CodeGen/X86/SIMD/notvunpcklps.ll
Normal file
20
test/CodeGen/X86/SIMD/notvunpcklps.ll
Normal file
@ -0,0 +1,20 @@
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; RUN: llc < %s -mattr=+avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @try_([2 x <8 x float>]* noalias %incarray, [2 x <8 x float>]* noalias %incarrayb ) {
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enmtry:
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%incarray1 = alloca [2 x <8 x float>]*, align 8
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%incarrayb1 = alloca [2 x <8 x float>]*, align 8
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%carray = alloca [2 x <8 x float>], align 16
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%r = getelementptr [2 x <8 x float>]* %incarray, i32 0, i32 0
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%rb = getelementptr [2 x <8 x float>]* %incarrayb, i32 0, i32 0
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%r3 = load <8 x float>* %r, align 8
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%r4 = load <8 x float>* %rb, align 8
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%r8 = shufflevector <8 x float> %r3, <8 x float> %r4, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x float>> [#uses=1]
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; CHECK-NOT: vunpcklps
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%r9 = getelementptr [2 x <8 x float>]* %carray, i32 0, i32 0
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store <8 x float> %r8, <8 x float>* %r9, align 4
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ret void
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}
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20
test/CodeGen/X86/SIMD/vunpcklpd.ll
Normal file
20
test/CodeGen/X86/SIMD/vunpcklpd.ll
Normal file
@ -0,0 +1,20 @@
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; RUN: llc < %s -mattr=+avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @try_([2 x <4 x double>]* noalias %incarray, [2 x <4 x double>]* noalias %incarrayb ) {
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entry:
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%incarray1 = alloca [2 x <4 x double>]*, align 8
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%incarrayb1 = alloca [2 x <4 x double>]*, align 8
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%carray = alloca [2 x <4 x double>], align 16
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%r = getelementptr [2 x <4 x double>]* %incarray, i32 0, i32 0
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%rb = getelementptr [2 x <4 x double>]* %incarrayb, i32 0, i32 0
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%r3 = load <4 x double>* %r, align 8
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%r4 = load <4 x double>* %rb, align 8
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%r11 = shufflevector <4 x double> %r3, <4 x double> %r4, <4 x i32> < i32 0, i32 4, i32 2, i32 6 > ; <<4 x double>> [#uses=1]
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; CHECK: vunpcklpd
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%r12 = getelementptr [2 x <4 x double>]* %carray, i32 0, i32 1
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store <4 x double> %r11, <4 x double>* %r12, align 4
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ret void
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}
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20
test/CodeGen/X86/SIMD/vunpcklps.ll
Normal file
20
test/CodeGen/X86/SIMD/vunpcklps.ll
Normal file
@ -0,0 +1,20 @@
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; RUN: llc < %s -mattr=+avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @try_([2 x <8 x float>]* noalias %incarray, [2 x <8 x float>]* noalias %incarrayb ) {
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entry:
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%incarray1 = alloca [2 x <8 x float>]*, align 8
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%incarrayb1 = alloca [2 x <8 x float>]*, align 8
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%carray = alloca [2 x <8 x float>], align 16
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%r = getelementptr [2 x <8 x float>]* %incarray, i32 0, i32 0
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%rb = getelementptr [2 x <8 x float>]* %incarrayb, i32 0, i32 0
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%r3 = load <8 x float>* %r, align 8
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%r4 = load <8 x float>* %rb, align 8
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%r11 = shufflevector <8 x float> %r3, <8 x float> %r4, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13 > ; <<8 x float>> [#uses=1]
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; CHECK: vunpcklps
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%r12 = getelementptr [2 x <8 x float>]* %carray, i32 0, i32 1
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store <8 x float> %r11, <8 x float>* %r12, align 4
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ret void
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}
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