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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Added new X86 patterns to select SSE scalar fp arithmetic instructions from
a vector packed single/double fp operation followed by a vector insert.
The effect is that the backend coverts the packed fp instruction
followed by a vectro insert into a SSE or AVX scalar fp instruction.
For example, given the following code:
__m128 foo(__m128 A, __m128 B) {
__m128 C = A + B;
return (__m128) {c[0], a[1], a[2], a[3]};
}
previously we generated:
addps %xmm0, %xmm1
movss %xmm1, %xmm0
we now generate:
addss %xmm1, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
b4605d4d4b
commit
a29b054e7a
@ -3142,6 +3142,89 @@ let AddedComplexity = 20, Predicates = [HasAVX] in {
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(VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
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}
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// Patterns used to select SSE scalar fp arithmetic instructions from
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// a vector packed single/double fp operation followed by a vector insert.
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//
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// The effect is that the backend converts the packed fp instruction
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// followed by a vector insert into a single SSE scalar fp instruction.
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//
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// For example, given the following code:
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// __m128 foo(__m128 A, __m128 B) {
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// __m128 C = A + B;
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// return (__m128) {c[0], a[1], a[2], a[3]};
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// }
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//
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// previously we generated:
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// addps %xmm0, %xmm1
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// movss %xmm1, %xmm0
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//
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// we now generate:
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// addss %xmm1, %xmm0
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def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
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(fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
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(ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
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def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
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(fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
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(SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
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def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
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(fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
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(MULSSrr_Int v4f32:$dst, v4f32:$src)>;
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def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
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(fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
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(DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
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let Predicates = [HasSSE2] in {
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// SSE2 patterns to select scalar double-precision fp arithmetic instructions
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// from a packed double-precision fp instruction plus movsd.
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
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(fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
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(ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
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(fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
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(SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
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(fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
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(MULSDrr_Int v2f64:$dst, v2f64:$src)>;
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
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(fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
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(DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
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}
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let AddedComplexity = 20, Predicates = [HasAVX] in {
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// The following patterns select AVX Scalar single/double precision fp
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// arithmetic instructions from a packed single precision fp instruction
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// plus movss/movsd.
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// The 'AddedComplexity' is required to give them higher priority over
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// the equivalent SSE/SSE2 patterns.
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def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
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(fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
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(VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
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def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
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(fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
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(VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
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def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
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(fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
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(VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
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def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
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(fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
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(VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
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(fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
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(VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
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(fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
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(VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
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(fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
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(VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
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(fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
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(VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
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}
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/// Unop Arithmetic
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/// In addition, we also have a special variant of the scalar form here to
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/// represent the associated intrinsic operation. This form is unlike the
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215
test/CodeGen/X86/sse-scalar-fp-arith-2.ll
Normal file
215
test/CodeGen/X86/sse-scalar-fp-arith-2.ll
Normal file
@ -0,0 +1,215 @@
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; RUN: llc -mtriple=x86_64-pc-linux -mcpu=corei7 < %s | FileCheck -check-prefix=CHECK -check-prefix=SSE2 %s
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; RUN: llc -mtriple=x86_64-pc-linux -mattr=-sse4.1 -mcpu=corei7 < %s | FileCheck -check-prefix=CHECK -check-prefix=SSE2 %s
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; RUN: llc -mtriple=x86_64-pc-linux -mcpu=corei7-avx < %s | FileCheck -check-prefix=CHECK -check-prefix=AVX %s
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; Ensure that the backend selects SSE/AVX scalar fp instructions
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; from a packed fp instrution plus a vector insert.
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define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
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%1 = fadd <4 x float> %a, %b
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%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test_add_ss
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; SSE2: addss %xmm1, %xmm0
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; AVX: vaddss %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test_sub_ss(<4 x float> %a, <4 x float> %b) {
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%1 = fsub <4 x float> %a, %b
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%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test_sub_ss
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; SSE2: subss %xmm1, %xmm0
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; AVX: vsubss %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test_mul_ss(<4 x float> %a, <4 x float> %b) {
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%1 = fmul <4 x float> %a, %b
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%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test_mul_ss
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; SSE2: mulss %xmm1, %xmm0
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; AVX: vmulss %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {
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%1 = fdiv <4 x float> %a, %b
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%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test_div_ss
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; SSE2: divss %xmm1, %xmm0
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; AVX: vdivss %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
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%1 = fadd <2 x double> %a, %b
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%2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %2
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}
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; CHECK-LABEL: test_add_sd
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; SSE2: addsd %xmm1, %xmm0
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; AVX: vaddsd %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test_sub_sd(<2 x double> %a, <2 x double> %b) {
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%1 = fsub <2 x double> %a, %b
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%2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %2
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}
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; CHECK-LABEL: test_sub_sd
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; SSE2: subsd %xmm1, %xmm0
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; AVX: vsubsd %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test_mul_sd(<2 x double> %a, <2 x double> %b) {
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%1 = fmul <2 x double> %a, %b
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%2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %2
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}
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; CHECK-LABEL: test_mul_sd
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; SSE2: mulsd %xmm1, %xmm0
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; AVX: vmulsd %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
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%1 = fdiv <2 x double> %a, %b
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%2 = shufflevector <2 x double> %1, <2 x double> %a, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %2
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}
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; CHECK-LABEL: test_div_sd
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; SSE2: divsd %xmm1, %xmm0
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; AVX: vdivsd %xmm1, %xmm0, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <4 x float> @test2_add_ss(<4 x float> %a, <4 x float> %b) {
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%1 = fadd <4 x float> %b, %a
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%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test2_add_ss
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; SSE2: addss %xmm0, %xmm1
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; AVX: vaddss %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test2_sub_ss(<4 x float> %a, <4 x float> %b) {
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%1 = fsub <4 x float> %b, %a
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%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test2_sub_ss
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; SSE2: subss %xmm0, %xmm1
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; AVX: vsubss %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test2_mul_ss(<4 x float> %a, <4 x float> %b) {
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%1 = fmul <4 x float> %b, %a
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%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test2_mul_ss
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; SSE2: mulss %xmm0, %xmm1
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; AVX: vmulss %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <4 x float> @test2_div_ss(<4 x float> %a, <4 x float> %b) {
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%1 = fdiv <4 x float> %b, %a
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%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %2
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}
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; CHECK-LABEL: test2_div_ss
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; SSE2: divss %xmm0, %xmm1
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; AVX: vdivss %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movss
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; CHECK: ret
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define <2 x double> @test2_add_sd(<2 x double> %a, <2 x double> %b) {
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%1 = fadd <2 x double> %b, %a
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%2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %2
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}
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; CHECK-LABEL: test2_add_sd
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; SSE2: addsd %xmm0, %xmm1
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; AVX: vaddsd %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test2_sub_sd(<2 x double> %a, <2 x double> %b) {
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%1 = fsub <2 x double> %b, %a
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%2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %2
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}
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; CHECK-LABEL: test2_sub_sd
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; SSE2: subsd %xmm0, %xmm1
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; AVX: vsubsd %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test2_mul_sd(<2 x double> %a, <2 x double> %b) {
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%1 = fmul <2 x double> %b, %a
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%2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %2
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}
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; CHECK-LABEL: test2_mul_sd
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; SSE2: mulsd %xmm0, %xmm1
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; AVX: vmulsd %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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define <2 x double> @test2_div_sd(<2 x double> %a, <2 x double> %b) {
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%1 = fdiv <2 x double> %b, %a
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%2 = shufflevector <2 x double> %1, <2 x double> %b, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %2
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}
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; CHECK-LABEL: test2_div_sd
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; SSE2: divsd %xmm0, %xmm1
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; AVX: vdivsd %xmm0, %xmm1, %xmm0
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; CHECK-NOT: movsd
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; CHECK: ret
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