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Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100650 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -306,23 +306,23 @@ def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
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//
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def VMOVRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
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IIC_VMOVSI, "vmov", "\t$dst, $src",
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IIC_fpMOVSI, "vmov", "\t$dst, $src",
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[(set GPR:$dst, (bitconvert SPR:$src))]>;
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def VMOVSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
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IIC_VMOVIS, "vmov", "\t$dst, $src",
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IIC_fpMOVIS, "vmov", "\t$dst, $src",
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[(set SPR:$dst, (bitconvert GPR:$src))]>;
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def VMOVRRD : AVConv3I<0b11000101, 0b1011,
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(outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
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IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src",
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IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src",
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[/* FIXME: Can't write pattern for multiple result instr*/]> {
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let Inst{7-6} = 0b00;
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}
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def VMOVRRS : AVConv3I<0b11000101, 0b1010,
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(outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
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IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
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IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{7-6} = 0b00;
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}
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@ -332,14 +332,14 @@ def VMOVRRS : AVConv3I<0b11000101, 0b1010,
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def VMOVDRR : AVConv5I<0b11000100, 0b1011,
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(outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
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IIC_VMOVID, "vmov", "\t$dst, $src1, $src2",
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IIC_fpMOVID, "vmov", "\t$dst, $src1, $src2",
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[(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]> {
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let Inst{7-6} = 0b00;
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}
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def VMOVSRR : AVConv5I<0b11000100, 0b1010,
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(outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
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IIC_VMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
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IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{7-6} = 0b00;
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}
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@ -77,6 +77,10 @@ def IIC_fpCVTIS : InstrItinClass;
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def IIC_fpCVTID : InstrItinClass;
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def IIC_fpCVTSI : InstrItinClass;
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def IIC_fpCVTDI : InstrItinClass;
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def IIC_fpMOVIS : InstrItinClass;
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def IIC_fpMOVID : InstrItinClass;
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def IIC_fpMOVSI : InstrItinClass;
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def IIC_fpMOVDI : InstrItinClass;
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def IIC_fpALU32 : InstrItinClass;
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def IIC_fpALU64 : InstrItinClass;
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def IIC_fpMUL32 : InstrItinClass;
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@ -753,7 +753,34 @@ def CortexA9Itineraries : ProcessorItineraries<[
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InstrItinData<IIC_fpSQRT64, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
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InstrStage2<33, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<28, [FU_NPipe]>], [32, 1]>
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InstrStage<28, [FU_NPipe]>], [32, 1]>,
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//
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// Integer to Single-precision Move
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InstrItinData<IIC_fpMOVIS, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
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// Extra 1 latency cycle since wbck is 2 cycles
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InstrStage2<3, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [1, 1]>,
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//
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// Integer to Double-precision Move
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InstrItinData<IIC_fpMOVID, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
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// Extra 1 latency cycle since wbck is 2 cycles
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InstrStage2<3, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [1, 1, 1]>,
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//
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// Single-precision to Integer Move
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InstrItinData<IIC_fpMOVSI, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
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InstrStage2<2, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [1, 1]>,
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//
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// Double-precision to Integer Move
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InstrItinData<IIC_fpMOVDI, [InstrStage2<1, [FU_DRegsVFP], 0, Required>,
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InstrStage2<2, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [1, 1, 1]>
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]>;
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