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Fix some release-assert warnings

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61244 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-12-19 17:03:38 +00:00
parent 2f6fea90a5
commit a33649e98c
2 changed files with 10 additions and 10 deletions
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8
lib/CodeGen/MachOWriter.cpp
View File

@ -264,8 +264,8 @@ void MachOCodeEmitter::emitConstantPool(MachineConstantPool *MCP) {
if (CP.empty()) return;
// FIXME: handle PIC codegen
bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
assert(!isPIC && "PIC codegen not yet handled for mach-o jump tables!");
assert(TM.getRelocationModel() != Reloc::PIC_ &&
"PIC codegen not yet handled for mach-o jump tables!");
// Although there is no strict necessity that I am aware of, we will do what
// gcc for OS X does and put each constant pool entry in a section of constant
@ -305,8 +305,8 @@ void MachOCodeEmitter::emitJumpTables(MachineJumpTableInfo *MJTI) {
if (JT.empty()) return;
// FIXME: handle PIC codegen
bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
assert(!isPIC && "PIC codegen not yet handled for mach-o jump tables!");
assert(TM.getRelocationModel() != Reloc::PIC_ &&
"PIC codegen not yet handled for mach-o jump tables!");
MachOWriter::MachOSection *Sec = MOW.getJumpTableSection();
unsigned TextSecIndex = MOW.getTextSection()->Index;

12
lib/Target/X86/X86FastISel.cpp
View File

@ -1219,14 +1219,14 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
case CCValAssign::SExt: {
bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
Arg, ArgVT, Arg);
assert(Emitted && "Failed to emit a sext!");
assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
ArgVT = VA.getLocVT();
break;
}
case CCValAssign::ZExt: {
bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
Arg, ArgVT, Arg);
assert(Emitted && "Failed to emit a zext!");
assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
ArgVT = VA.getLocVT();
break;
}
@ -1240,7 +1240,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
Arg, ArgVT, Arg);
assert(Emitted && "Failed to emit a aext!");
assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
ArgVT = VA.getLocVT();
break;
}
@ -1250,7 +1250,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
Arg, RC, RC);
assert(Emitted && "Failed to emit a copy instruction!");
assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
RegArgs.push_back(VA.getLocReg());
} else {
unsigned LocMemOffset = VA.getLocMemOffset();
@ -1277,7 +1277,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
TargetRegisterClass *RC = X86::GR32RegisterClass;
unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
assert(Emitted && "Failed to emit a copy instruction!");
assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
}
// Issue the call.
@ -1328,7 +1328,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
unsigned ResultReg = createResultReg(DstRC);
bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
RVLocs[0].getLocReg(), DstRC, SrcRC);
assert(Emitted && "Failed to emit a copy instruction!");
assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
if (CopyVT != RVLocs[0].getValVT()) {
// Round the F80 the right size, which also moves to the appropriate xmm
// register. This is accomplished by storing the F80 value in memory and