Encode predict = 1 by default, because the Sparc assembler does this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7181 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2003-07-15 21:26:49 +00:00
parent f6e5217b54
commit a34b619f67

View File

@ -38,21 +38,21 @@ class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
bits<2> cc;
bits<19> disp;
bit predict;
bit predict = 1;
bit annul;
set Name = name;
set Inst{29} = annul;
set Inst{28-25} = cond;
set Inst{21-20} = cc;
set Inst{19} = predict;
set Inst{19} = 1; // predict;
set Inst{18-0} = disp;
}
class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
bits<5> rs1;
bits<16> disp;
bit predict;
bit predict = 1;
bit annul;
set Name = name;
@ -60,7 +60,7 @@ class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
set Inst{28} = 0;
set Inst{27-25} = rcond;
set Inst{21-20} = disp{15-14};
set Inst{19} = predict;
set Inst{19} = 1; // predict;
set Inst{18-14} = rs1;
set Inst{13-0 } = disp{13-0};
}