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Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-10-07 22:57:01 +00:00
parent 9f3a559dff
commit a4288080e6
4 changed files with 17 additions and 0 deletions
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1
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -1357,6 +1357,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4i16: Opc = ARM::VLD2d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD2d32; break;
case MVT::v1i64: Opc = ARM::VLD2d64; break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };

3
lib/Target/ARM/ARMInstrNEON.td
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@ -193,6 +193,9 @@ class VLD2Q<bits<4> op7_4, string OpcodeStr>
def VLD2d8 : VLD2D<0b0000, "vld2.8">;
def VLD2d16 : VLD2D<0b0100, "vld2.16">;
def VLD2d32 : VLD2D<0b1000, "vld2.32">;
def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
(ins addrmode6:$addr), IIC_VLD1,
"vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>;
def VLD2q8 : VLD2Q<0b0000, "vld2.8">;
def VLD2q16 : VLD2Q<0b0100, "vld2.16">;

1
lib/Target/ARM/NEONPreAllocPass.cpp
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@ -49,6 +49,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
case ARM::VLD2d8:
case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d64:
case ARM::VLD2LNd8:
case ARM::VLD2LNd16:
case ARM::VLD2LNd32:

12
test/CodeGen/ARM/vld2.ll
View File

@ -4,6 +4,7 @@
%struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> }
%struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> }
%struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
%struct.__neon_int64x1x2_t = type { <1 x i64>, <1 x i64> }
%struct.__neon_int8x16x2_t = type { <16 x i8>, <16 x i8> }
%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
@ -50,6 +51,16 @@ define <2 x float> @vld2f(float* %A) nounwind {
ret <2 x float> %tmp4
}
define <1 x i64> @vld2i64(i64* %A) nounwind {
;CHECK: vld2i64:
;CHECK: vld1.64
%tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i64* %A)
%tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
%tmp4 = add <1 x i64> %tmp2, %tmp3
ret <1 x i64> %tmp4
}
define <16 x i8> @vld2Qi8(i8* %A) nounwind {
;CHECK: vld2Qi8:
;CHECK: vld2.8
@ -94,6 +105,7 @@ declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8*) nounwind readonl
declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8*) nounwind readonly
declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8*) nounwind readonly
declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8*) nounwind readonly
declare %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8*) nounwind readonly
declare %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8*) nounwind readonly
declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8*) nounwind readonly