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Cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57344 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -44,15 +44,15 @@ public:
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bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Offset);
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelect();
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virtual const char *getPassName() const {
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return "SPARC DAG->DAG Pattern Instruction Selection";
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}
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}
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// Include the pieces autogenerated from the target description.
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#include "SparcGenDAGISel.inc"
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};
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@ -62,7 +62,7 @@ public:
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void SparcDAGToDAGISel::InstructionSelect() {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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SelectRoot();
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CurDAG->RemoveDeadNodes();
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@ -78,11 +78,11 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (Predicate_simm13(CN)) {
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if (FrameIndexSDNode *FIN =
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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// Constant offset from frame ref.
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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@ -115,7 +115,7 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).getNode()))
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@ -147,7 +147,7 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
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SDValue DivRHS = N->getOperand(1);
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AddToISelQueue(DivLHS);
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AddToISelQueue(DivRHS);
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// Set the Y register to the high-part.
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SDValue TopPart;
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if (N->getOpcode() == ISD::SDIV) {
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@ -163,7 +163,7 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
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return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
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TopPart);
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}
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}
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case ISD::MULHU:
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case ISD::MULHS: {
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// FIXME: Handle mul by immediate.
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@ -179,12 +179,12 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
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return NULL;
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}
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}
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return SelectCode(Op);
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}
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/// createSparcISelDag - This pass converts a legalized DAG into a
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/// createSparcISelDag - This pass converts a legalized DAG into a
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/// SPARC-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
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