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[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
2014-04-09 14:42:11 +00:00
parent a5b549e03c
commit a493b7786a
3 changed files with 49 additions and 33 deletions
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29
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
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@@ -854,6 +854,14 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
switch (Inst.getOpcode()) {
default:
return Fail;
case ARM64::ADDWrs:
case ARM64::ADDSWrs:
case ARM64::SUBWrs:
case ARM64::SUBSWrs:
// if shift == '11' then ReservedValue()
if (shiftHi == 0x3)
return Fail;
// Deliberate fallthrough
case ARM64::ANDWrs:
case ARM64::ANDSWrs:
case ARM64::BICWrs:
@@ -861,16 +869,23 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
case ARM64::ORRWrs:
case ARM64::ORNWrs:
case ARM64::EORWrs:
case ARM64::EONWrs:
case ARM64::ADDWrs:
case ARM64::ADDSWrs:
case ARM64::SUBWrs:
case ARM64::SUBSWrs: {
case ARM64::EONWrs: {
// if sf == '0' and imm6<5> == '1' then ReservedValue()
if (shiftLo >> 5 == 1)
return Fail;
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break;
}
case ARM64::ADDXrs:
case ARM64::ADDSXrs:
case ARM64::SUBXrs:
case ARM64::SUBSXrs:
// if shift == '11' then ReservedValue()
if (shiftHi == 0x3)
return Fail;
// Deliberate fallthrough
case ARM64::ANDXrs:
case ARM64::ANDSXrs:
case ARM64::BICXrs:
@@ -879,10 +894,6 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
case ARM64::ORNXrs:
case ARM64::EORXrs:
case ARM64::EONXrs:
case ARM64::ADDXrs:
case ARM64::ADDSXrs:
case ARM64::SUBXrs:
case ARM64::SUBSXrs:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);