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LLVM backend for 6502
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Bradley Smith a493b7786a [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:11 +00:00
autoconf ARM64: initial backend import 2014-03-29 10:18:08 +00:00
bindings
cmake Add support for building LLVM on FreeBSD 9.2 2014-04-09 11:43:34 +00:00
docs [docs] VCS contains a record of authorship 2014-04-08 21:12:56 +00:00
examples
include SLPVectorizer: Only vectorize intrinsics whose operands are widened equally 2014-04-09 14:20:47 +00:00
lib [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 2014-04-09 14:42:11 +00:00
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test [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 2014-04-09 14:42:11 +00:00
tools [yaml2obj][ELF] Rename class SectionNameToIdxMap => NameToIdxMap. It can 2014-04-06 09:02:55 +00:00
unittests Revert "YAMLIO: Encode ambiguous hex strings explicitly" 2014-04-09 14:35:17 +00:00
utils When a CHECK-NEXT fails because there was no match on the next line, include 2014-04-07 17:09:53 +00:00
.arcconfig Updated phabricator server. 2014-04-07 03:57:04 +00:00
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.gitignore
CMakeLists.txt Add ability to disable building LLVM utils 2014-04-02 22:49:58 +00:00
CODE_OWNERS.TXT ARM Linux support 2014-04-02 23:03:28 +00:00
configure ARM64: initial backend import 2014-03-29 10:18:08 +00:00
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README.txt 

Low Level Virtual Machine (LLVM)
================================

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