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Add bunch of 32-bit patterns... Uffff :)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75926 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
2009-07-16 13:42:31 +00:00
parent 0692fabb4e
commit a51752cbea
17 changed files with 527 additions and 9 deletions
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lib/Target/SystemZ/SystemZInstrInfo.cpp
+14 -2
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@@ -50,10 +50,21 @@ bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc();
if (DestRC == SrcRC) {
// Determine if DstRC and SrcRC have a common superclass.
const TargetRegisterClass *CommonRC = DestRC;
if (DestRC == SrcRC)
/* Same regclass for source and dest */;
else if (CommonRC->hasSuperClass(SrcRC))
CommonRC = SrcRC;
else if (!CommonRC->hasSubClass(SrcRC))
CommonRC = 0;
if (CommonRC) {
unsigned Opc;
if (DestRC == &SystemZ::GR64RegClass) {
if (CommonRC == &SystemZ::GR64RegClass) {
Opc = SystemZ::MOV64rr;
} else if (CommonRC == &SystemZ::GR32RegClass) {
Opc = SystemZ::MOV32rr;
} else {
return false;
}
@@ -74,6 +85,7 @@ SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
switch (MI.getOpcode()) {
default:
return false;
case SystemZ::MOV32rr:
case SystemZ::MOV64rr:
assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isReg() &&