mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
Add bunch of 32-bit patterns... Uffff :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75926 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
0692fabb4e
commit
a51752cbea
@ -13,6 +13,9 @@
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// SystemZ Return Value Calling Convention
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//===----------------------------------------------------------------------===//
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def RetCC_SystemZ : CallingConv<[
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// Promote i8/i16/i32 arguments to i64.
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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// i64 is returned in register R2
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CCIfType<[i64], CCAssignToReg<[R2D]>>
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]>;
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@ -39,6 +39,7 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
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// Set up the register classes.
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addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
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addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
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// Compute derived properties from the register classes
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@ -191,12 +192,21 @@ SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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SDValue ResValue = Op.getOperand(i*2+1);
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assert(VA.isRegLoc() && "Can only return in registers!");
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// If this is an 8/16/32-bit value, it is really should be passed promoted
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// to 64 bits.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
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else if (VA.getLocInfo() == CCValAssign::AExt)
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ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
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// ISD::RET => ret chain, (regnum1,val1), ...
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// So i*2+1 index only the regnums
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
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Op.getOperand(i*2+1), Flag);
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad.
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@ -50,10 +50,21 @@ bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC == SrcRC) {
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// Determine if DstRC and SrcRC have a common superclass.
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const TargetRegisterClass *CommonRC = DestRC;
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if (DestRC == SrcRC)
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/* Same regclass for source and dest */;
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else if (CommonRC->hasSuperClass(SrcRC))
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CommonRC = SrcRC;
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else if (!CommonRC->hasSubClass(SrcRC))
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CommonRC = 0;
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if (CommonRC) {
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unsigned Opc;
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if (DestRC == &SystemZ::GR64RegClass) {
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if (CommonRC == &SystemZ::GR64RegClass) {
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Opc = SystemZ::MOV64rr;
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} else if (CommonRC == &SystemZ::GR32RegClass) {
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Opc = SystemZ::MOV32rr;
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} else {
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return false;
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}
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@ -74,6 +85,7 @@ SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
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switch (MI.getOpcode()) {
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default:
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return false;
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case SystemZ::MOV32rr:
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case SystemZ::MOV64rr:
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() &&
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@ -55,13 +55,13 @@ def HI32 : SDNodeXForm<imm, [{
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return getI32Imm(N->getZExtValue() >> 32);
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}]>;
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def i64ll16 : PatLeaf<(i64 imm), [{
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def i64ll16 : PatLeaf<(imm), [{
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// i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
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// bits set.
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return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
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}], LL16>;
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def i64lh16 : PatLeaf<(i64 imm), [{
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def i64lh16 : PatLeaf<(imm), [{
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// i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
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return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
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}], LH16>;
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@ -76,11 +76,18 @@ def i64hh16 : PatLeaf<(i64 imm), [{
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return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
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}], HH16>;
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def immSExt16 : PatLeaf<(i64 imm), [{
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def immSExt16 : PatLeaf<(imm), [{
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// immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
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// field.
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uint64_t val = N->getZExtValue();
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return ((int64_t)val == (int16_t)val);
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if (N->getValueType(0) == MVT::i64) {
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uint64_t val = N->getZExtValue();
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return ((int64_t)val == (int16_t)val);
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} else if (N->getValueType(0) == MVT::i32) {
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uint32_t val = N->getZExtValue();
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return ((int32_t)val == (int16_t)val);
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}
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return false;
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}]>;
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def immSExt32 : PatLeaf<(i64 imm), [{
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@ -115,13 +122,26 @@ let isReturn = 1, isTerminator = 1 in {
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// FIXME: Provide proper encoding!
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let neverHasSideEffects = 1 in {
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def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
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"lr\t{$dst, $src}",
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[]>;
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def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
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"lgr\t{$dst, $src}",
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[]>;
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}
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def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
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"lgfr\t{$dst, $src}",
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[(set GR64:$dst, (sext GR32:$src))]>;
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def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
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"llgfr\t{$dst, $src}",
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[(set GR64:$dst, (zext GR32:$src))]>;
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// FIXME: Provide proper encoding!
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins i32imm:$src),
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"lhi\t{$dst, $src}",
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[(set GR32:$dst, immSExt16:$src)]>;
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def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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"lghi\t{$dst, $src}",
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[(set GR64:$dst, immSExt16:$src)]>;
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@ -159,6 +179,10 @@ let Defs = [PSW] in {
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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// FIXME: Provide proper encoding!
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def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"ar\t{$dst, $src2}",
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[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
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(implicit PSW)]>;
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def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"agr\t{$dst, $src2}",
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[(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
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@ -166,6 +190,14 @@ def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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}
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// FIXME: Provide proper encoding!
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def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"ahi\t{$dst, $src2}",
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[(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
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(implicit PSW)]>;
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def ADD32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"afi\t{$dst, $src2}",
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[(set GR32:$dst, (add GR32:$src1, imm:$src2)),
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(implicit PSW)]>;
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def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"aghi\t{$dst, $src2}",
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[(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
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@ -177,6 +209,9 @@ def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
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// FIXME: Provide proper encoding!
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def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"nr\t{$dst, $src2}",
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[(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
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def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"ngr\t{$dst, $src2}",
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[(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
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@ -205,11 +240,24 @@ def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
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// FIXME: Provide proper encoding!
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def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"or\t{$dst, $src2}",
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[(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
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def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"ogr\t{$dst, $src2}",
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[(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
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}
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def OR32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
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"oill\t{$dst, $src2}",
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[(set GR32:$dst, (or GR32:$src1, i64ll16:$src2))]>;
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def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
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"oilh\t{$dst, $src2}",
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[(set GR32:$dst, (or GR32:$src1, i64lh16:$src2))]>;
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def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"oilf\t{$dst, $src2}",
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[(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
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def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"oill\t{$dst, $src2}",
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[(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
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@ -231,6 +279,9 @@ def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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[(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
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// FIXME: Provide proper encoding!
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def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"sr\t{$dst, $src2}",
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[(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
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def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"sgr\t{$dst, $src2}",
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[(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
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@ -238,11 +289,18 @@ def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
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// FIXME: Provide proper encoding!
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def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"xr\t{$dst, $src2}",
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[(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
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def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"xgr\t{$dst, $src2}",
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[(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
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}
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def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"xilf\t{$dst, $src2}",
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[(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
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// FIXME: these 2 instructions seem to require extimm facility
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def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"xilf\t{$dst, $src2}",
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@ -253,3 +311,25 @@ def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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} // Defs = [PSW]
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} // isTwoAddress = 1
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns.
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//===----------------------------------------------------------------------===//
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// anyext
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def : Pat<(i64 (anyext GR32:$src)),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
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//===----------------------------------------------------------------------===//
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// Peepholes.
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//===----------------------------------------------------------------------===//
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// FIXME: use add/sub tricks with 32678/-32768
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// trunc patterns
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def : Pat<(i32 (trunc GR64:$src)),
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(EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
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// sext_inreg patterns
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def : Pat<(sext_inreg GR64:$src, i32),
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(MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
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@ -135,6 +135,7 @@ def GR64 : RegisterClass<"SystemZ", [i64], 64,
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// Volatile, but not allocable
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R14D, R15D]>
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{
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let SubRegClassList = [GR32];
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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42
test/CodeGen/SystemZ/03-RetAddImmSubreg.ll
Normal file
42
test/CodeGen/SystemZ/03-RetAddImmSubreg.ll
Normal file
@ -0,0 +1,42 @@
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; RUN: llvm-as < %s | llc -march=systemz | grep ahi | count 3
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; RUN: llvm-as < %s | llc -march=systemz | grep afi | count 3
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; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 4
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; RUN: llvm-as < %s | llc -march=systemz | grep llgfr | count 2
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define i32 @foo1(i32 %a, i32 %b) {
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entry:
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%c = add i32 %a, 1
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ret i32 %c
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}
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define i32 @foo2(i32 %a, i32 %b) {
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entry:
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%c = add i32 %a, 131072
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ret i32 %c
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}
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define i32 @foo3(i32 %a, i32 %b) zeroext {
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entry:
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%c = add i32 %a, 1
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ret i32 %c
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}
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define i32 @foo4(i32 %a, i32 %b) zeroext {
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entry:
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%c = add i32 %a, 131072
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ret i32 %c
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}
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define i32 @foo5(i32 %a, i32 %b) signext {
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entry:
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%c = add i32 %a, 1
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ret i32 %c
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}
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define i32 @foo6(i32 %a, i32 %b) signext {
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entry:
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%c = add i32 %a, 131072
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ret i32 %c
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}
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22
test/CodeGen/SystemZ/03-RetAddSubreg.ll
Normal file
22
test/CodeGen/SystemZ/03-RetAddSubreg.ll
Normal file
@ -0,0 +1,22 @@
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; RUN: llvm-as < %s | llc -march=systemz | grep ar | count 3
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; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 2
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; RUN: llvm-as < %s | llc -march=systemz | grep llgfr | count 1
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define i32 @foo(i32 %a, i32 %b) {
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entry:
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%c = add i32 %a, %b
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ret i32 %c
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}
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define i32 @foo1(i32 %a, i32 %b) zeroext {
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entry:
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%c = add i32 %a, %b
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ret i32 %c
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}
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define i32 @foo2(i32 %a, i32 %b) signext {
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entry:
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%c = add i32 %a, %b
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ret i32 %c
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}
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39
test/CodeGen/SystemZ/03-RetAndImmSubreg.ll
Normal file
39
test/CodeGen/SystemZ/03-RetAndImmSubreg.ll
Normal file
@ -0,0 +1,39 @@
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; RUN: llvm-as < %s | llc -march=systemz | grep nill | count 3
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; RUN: llvm-as < %s | llc -march=systemz | grep nilh | count 3
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define i32 @foo1(i32 %a, i32 %b) {
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entry:
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%c = and i32 %a, 1
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ret i32 %c
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}
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define i32 @foo2(i32 %a, i32 %b) {
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entry:
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%c = and i32 %a, 131072
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ret i32 %c
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}
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define i32 @foo3(i32 %a, i32 %b) zeroext {
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entry:
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%c = and i32 %a, 1
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ret i32 %c
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}
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define i32 @foo4(i32 %a, i32 %b) signext {
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entry:
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%c = and i32 %a, 131072
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ret i32 %c
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}
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define i32 @foo5(i32 %a, i32 %b) zeroext {
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entry:
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%c = and i32 %a, 1
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ret i32 %c
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}
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define i32 @foo6(i32 %a, i32 %b) signext {
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entry:
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%c = and i32 %a, 131072
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ret i32 %c
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}
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20
test/CodeGen/SystemZ/03-RetAndSubreg.ll
Normal file
20
test/CodeGen/SystemZ/03-RetAndSubreg.ll
Normal file
@ -0,0 +1,20 @@
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; RUN: llvm-as < %s | llc -march=systemz | grep ngr | count 3
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|
||||
define i32 @foo(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = and i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo1(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = and i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo2(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = and i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
19
test/CodeGen/SystemZ/03-RetArgSubreg.ll
Normal file
19
test/CodeGen/SystemZ/03-RetArgSubreg.ll
Normal file
@ -0,0 +1,19 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgr | count 2
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
|
||||
|
||||
|
||||
define i32 @foo(i32 %a, i32 %b) {
|
||||
entry:
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
define i32 @foo1(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
define i32 @foo2(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
ret i32 %b
|
||||
}
|
||||
42
test/CodeGen/SystemZ/03-RetImmSubreg.ll
Normal file
42
test/CodeGen/SystemZ/03-RetImmSubreg.ll
Normal file
@ -0,0 +1,42 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lghi | count 2
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llill | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llilh | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfi | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 2
|
||||
|
||||
|
||||
define i32 @foo1() {
|
||||
entry:
|
||||
ret i32 1
|
||||
}
|
||||
|
||||
define i32 @foo2() {
|
||||
entry:
|
||||
ret i32 65535
|
||||
}
|
||||
|
||||
define i32 @foo3() {
|
||||
entry:
|
||||
ret i32 131072
|
||||
}
|
||||
|
||||
define i32 @foo4() {
|
||||
entry:
|
||||
ret i32 65537
|
||||
}
|
||||
|
||||
define i32 @foo5() {
|
||||
entry:
|
||||
ret i32 4294967295
|
||||
}
|
||||
|
||||
define i32 @foo6() zeroext {
|
||||
entry:
|
||||
ret i32 4294967295
|
||||
}
|
||||
|
||||
define i32 @foo7() signext {
|
||||
entry:
|
||||
ret i32 4294967295
|
||||
}
|
||||
|
||||
60
test/CodeGen/SystemZ/03-RetOrImmSubreg.ll
Normal file
60
test/CodeGen/SystemZ/03-RetOrImmSubreg.ll
Normal file
@ -0,0 +1,60 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep oill | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep oilh | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep oilf | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llgfr | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 6
|
||||
|
||||
define i32 @foo1(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = or i32 %a, 1
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo2(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = or i32 %a, 131072
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo7(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = or i32 %a, 123456
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo3(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = or i32 %a, 1
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo8(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = or i32 %a, 123456
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo4(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = or i32 %a, 131072
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo5(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = or i32 %a, 1
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo6(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = or i32 %a, 131072
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo9(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = or i32 %a, 123456
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
23
test/CodeGen/SystemZ/03-RetOrSubreg.ll
Normal file
23
test/CodeGen/SystemZ/03-RetOrSubreg.ll
Normal file
@ -0,0 +1,23 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep ogr | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
|
||||
|
||||
|
||||
define i32 @foo(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = or i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo1(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = or i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo2(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = or i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
42
test/CodeGen/SystemZ/03-RetSubImmSubreg.ll
Normal file
42
test/CodeGen/SystemZ/03-RetSubImmSubreg.ll
Normal file
@ -0,0 +1,42 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep ahi | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep afi | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 4
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llgfr | count 2
|
||||
|
||||
|
||||
define i32 @foo1(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = sub i32 %a, 1
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo2(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = sub i32 %a, 131072
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo3(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = sub i32 %a, 1
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo4(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = sub i32 %a, 131072
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo5(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = sub i32 %a, 1
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo6(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = sub i32 %a, 131072
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
22
test/CodeGen/SystemZ/03-RetSubSubreg.ll
Normal file
22
test/CodeGen/SystemZ/03-RetSubSubreg.ll
Normal file
@ -0,0 +1,22 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep sr | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llgfr | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 2
|
||||
|
||||
define i32 @foo(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = sub i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo1(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = sub i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo2(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = sub i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
58
test/CodeGen/SystemZ/03-RetXorImmSubreg.ll
Normal file
58
test/CodeGen/SystemZ/03-RetXorImmSubreg.ll
Normal file
@ -0,0 +1,58 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep xilf | count 9
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep llgfr | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 6
|
||||
|
||||
define i32 @foo1(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = xor i32 %a, 1
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo2(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = xor i32 %a, 131072
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo7(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = xor i32 %a, 123456
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo3(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = xor i32 %a, 1
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo8(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = xor i32 %a, 123456
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo4(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = xor i32 %a, 131072
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo5(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = xor i32 %a, 1
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo6(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = xor i32 %a, 131072
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo9(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = xor i32 %a, 123456
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
23
test/CodeGen/SystemZ/03-RetXorSubreg.ll
Normal file
23
test/CodeGen/SystemZ/03-RetXorSubreg.ll
Normal file
@ -0,0 +1,23 @@
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep xgr | count 3
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 1
|
||||
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
|
||||
|
||||
|
||||
define i32 @foo(i32 %a, i32 %b) {
|
||||
entry:
|
||||
%c = xor i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo1(i32 %a, i32 %b) zeroext {
|
||||
entry:
|
||||
%c = xor i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @foo2(i32 %a, i32 %b) signext {
|
||||
entry:
|
||||
%c = xor i32 %a, %b
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user