mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-27 15:57:13 +00:00
--added suggesting colors; call/ret arg handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@670 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka
parent
6b12936ac3
commit
a5ab9648a8
@ -4,12 +4,15 @@ LiveRangeInfo::LiveRangeInfo(const Method *const M,
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const TargetMachine& tm,
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vector<RegClass *> &RCL)
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: Meth(M), LiveRangeMap(),
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TM(tm), RegClassList(RCL)
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TM(tm), RegClassList(RCL),
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MRI( tm.getRegInfo()),
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CallRetInstrList()
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{ }
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// union two live ranges into one. The 2nd LR is deleted. Used for coalescing.
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// Note: the caller must make sure that L1 and L2 are distinct
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// Note: the caller must make sure that L1 and L2 are distinct and both
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// LRs don't have suggested colors
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void LiveRangeInfo::unionAndUpdateLRs(LiveRange *const L1, LiveRange *L2)
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{
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@ -24,6 +27,15 @@ void LiveRangeInfo::unionAndUpdateLRs(LiveRange *const L1, LiveRange *L2)
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L1->add( *L2It ); // add the var in L2 to L1
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LiveRangeMap[ *L2It ] = L1; // now the elements in L2 should map to L1
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}
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// Now if LROfDef(L1) has a suggested color, it will remain.
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// But, if LROfUse(L2) has a suggested color, the new range
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// must have the same color.
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if(L2->hasSuggestedColor())
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L1->setSuggestedColor( L2->getSuggestedColor() );
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delete ( L2 ); // delete L2 as it is no longer needed
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}
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@ -58,7 +70,7 @@ void LiveRangeInfo::constructLiveRanges()
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// create a temp machine op to find the register class of value
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//const MachineOperand Op(MachineOperand::MO_VirtualRegister);
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unsigned rcid = (TM.getRegInfo()).getRegClassIDOfValue( Val );
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unsigned rcid = MRI.getRegClassIDOfValue( Val );
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ArgRange->setRegClass(RegClassList[ rcid ] );
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@ -68,16 +80,24 @@ void LiveRangeInfo::constructLiveRanges()
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}
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}
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// Now suggest hardware registers for these method args
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MRI.suggestRegs4MethodArgs(Meth, *this);
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// Now find speical LLVM instructions (CALL, RET) and LRs in machine
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// instructions.
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// Now find all LRs for machine the instructions. A new LR will be created
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// only for defs in the machine instr since, we assume that all Values are
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// defined before they are used. However, there can be multiple defs for
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// the same Value in machine instructions.
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // go thru BBs in random order
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// Now find all LRs for machine the instructions. A new LR will be created
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// only for defs in the machine instr since, we assume that all Values are
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// defined before they are used. However, there can be multiple defs for
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// the same Value in machine instructions.
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator
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@ -87,12 +107,20 @@ void LiveRangeInfo::constructLiveRanges()
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for( ; MInstIterator != MIVec.end(); MInstIterator++) {
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const MachineInstr * MInst = *MInstIterator;
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// Now if the machine instruction has special operands that must be
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// set with a "suggested color", do it here.
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if( MRI.handleSpecialMInstr(MInst, *this, RegClassList) )
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continue;
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// iterate over MI operands to find defs
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for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); OpI++) {
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for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
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// delete later from here ************
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// delete later from here ************
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MachineOperand::MachineOperandType OpTyp =
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OpI.getMachineOperand().getOperandType();
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@ -104,11 +132,21 @@ void LiveRangeInfo::constructLiveRanges()
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// ************* to here
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// create a new LR iff this operand is a def
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if( OpI.isDef() ) {
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const Value *const Def = *OpI;
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// Only instruction values are accepted for live ranges here
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if( Def->getValueType() != Value::InstructionVal ) {
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cout << "\n**%%Error: Def is not an instruction val. Def=";
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printValue( Def ); cout << endl;
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continue;
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}
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LiveRange *DefRange = LiveRangeMap[Def];
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// see LR already there (because of multiple defs)
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@ -130,7 +168,7 @@ void LiveRangeInfo::constructLiveRanges()
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OpI.getMachineOperand().getOperandType();
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bool isCC = ( OpTy == MachineOperand::MO_CCRegister);
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unsigned rcid = (TM.getRegInfo()).getRegClassIDOfValue(
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unsigned rcid = MRI.getRegClassIDOfValue(
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OpI.getMachineOperand().getVRegValue(), isCC );
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@ -163,6 +201,42 @@ void LiveRangeInfo::constructLiveRanges()
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} // for all machine instructions in the BB
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} // for all BBs in method
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// go thru LLVM instructions in the basic block and suggest colors
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// for their args. Also record all CALL
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// instructions and Return instructions in the CallRetInstrList
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// This is done because since there are no reverse pointers in machine
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// instructions to find the llvm instruction, when we encounter a call
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// or a return whose args must be specailly colored (e.g., %o's for args)
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// We have to makes sure that all LRs of call/ret args are added before
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// doing this. But return value of call will not have a LR.
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BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // go thru BBs in random order
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BasicBlock::const_iterator InstIt = (*BBI)->begin();
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for( ; InstIt != (*BBI)->end() ; ++InstIt) {
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const Instruction *const CallRetI = *InstIt;
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unsigned OpCode = (CallRetI)->getOpcode();
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if( (OpCode == Instruction::Call) ) {
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CallRetInstrList.push_back(CallRetI );
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MRI.suggestRegs4CallArgs( (CallInst *) CallRetI, *this, RegClassList );
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}
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else if (OpCode == Instruction::Ret ) {
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CallRetInstrList.push_back( CallRetI );
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MRI.suggestReg4RetValue( (ReturnInst *) CallRetI, *this);
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}
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} // for each llvm instr in BB
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} // for all BBs in method
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if( DEBUG_RA)
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@ -183,7 +257,8 @@ void LiveRangeInfo::coalesceLRs()
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if the def and op are of the same type
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if the def and op do not interfere //i.e., not simultaneously live
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if (degree(LR of def) + degree(LR of op)) <= # avail regs
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merge2IGNodes(def, op) // i.e., merge 2 LRs
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if both LRs do not have suggested colors
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merge2IGNodes(def, op) // i.e., merge 2 LRs
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*/
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@ -253,8 +328,14 @@ void LiveRangeInfo::coalesceLRs()
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if( CombinedDegree <= RCOfDef->getNumOfAvailRegs() ) {
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RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
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unionAndUpdateLRs(LROfDef, LROfUse);
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// if both LRs do not have suggested colors
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if( ! (LROfDef->hasSuggestedColor() &&
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LROfUse->hasSuggestedColor() ) ) {
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RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
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unionAndUpdateLRs(LROfDef, LROfUse);
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}
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} // if combined degree is less than # of regs
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@ -289,7 +370,7 @@ void LiveRangeInfo::printLiveRanges()
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LiveRangeMapType::iterator HMI = LiveRangeMap.begin(); // hash map iterator
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cout << endl << "Printing Live Ranges from Hash Map:" << endl;
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for( ; HMI != LiveRangeMap.end() ; HMI ++ ) {
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if( (*HMI).first ) {
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if( (*HMI).first && (*HMI).second ) {
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cout <<" "; printValue((*HMI).first); cout << "\t: ";
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((*HMI).second)->printSet(); cout << endl;
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}
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@ -17,8 +17,6 @@ PhyRegAlloc::PhyRegAlloc(const Method *const M,
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Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
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MRI( tm.getRegInfo() ),
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NumOfRegClasses(MRI.getNumOfRegClasses()),
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CallInstrList(),
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RetInstrList(),
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AddedInstrMap()
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{
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@ -47,10 +45,18 @@ void PhyRegAlloc::createIGNodeListsAndIGs()
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LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
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for( ; HMI != HMIEnd ; ++HMI ) {
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if( (*HMI).first ) {
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LiveRange *L = (*HMI).second; // get the LiveRange
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LiveRange *L = (*HMI).second; // get the LiveRange
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if( (*HMI).first ) {
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if( !L) {
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if( DEBUG_RA) {
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cout << "\n*?!?Warning: Null liver range found for: ";
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printValue( (*HMI).first) ; cout << endl;
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}
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continue;
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}
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// if the Value * is not null, and LR
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// is not yet written to the IGNodeList
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if( !(L->getUserIGNode()) ) {
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@ -155,7 +161,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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const MachineInstr *const MInst = *MInstIterator;
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// get the LV set after the instruction
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@ -178,6 +184,8 @@ void PhyRegAlloc::buildInterferenceGraphs()
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} // for all machine instructions in BB
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#if 0
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// go thru LLVM instructions in the basic block and record all CALL
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// instructions and Return instructions in the CallInstrList
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// This is done because since there are no reverse pointers in machine
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@ -194,6 +202,9 @@ void PhyRegAlloc::buildInterferenceGraphs()
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else if( OpCode == Instruction::Ret )
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RetInstrList.push_back( *InstIt );
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}
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#endif
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} // for all BBs in method
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@ -257,7 +268,38 @@ void PhyRegAlloc::updateMachineCode()
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *const MInst = *MInstIterator;
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MachineInstr *MInst = *MInstIterator;
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// If there are instructions before to be added, add them now
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// ***TODO: Add InstrnsAfter as well
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if( AddedInstrMap[ MInst ] ) {
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vector<MachineInstr *> &IBef =
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(AddedInstrMap[MInst])->InstrnsBefore;
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if( ! IBef.empty() ) {
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vector<MachineInstr *>::iterator AdIt;
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for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
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cout << "*ADDED instr opcode: ";
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cout << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString;
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cout << endl;
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MInstIterator = MIVec.insert( MInstIterator, *AdIt );
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++MInstIterator;
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}
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}
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// restart from the topmost instruction added
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//MInst = *MInstIterator;
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}
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//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
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@ -289,8 +331,9 @@ void PhyRegAlloc::updateMachineCode()
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cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
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}
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Op.setRegForValue( -1 ); // mark register as invalid
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Op.setRegForValue( 1000 ); // mark register as invalid
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#if 0
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if( ((Val->getType())->isLabelType()) ||
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(Val->getValueType() == Value::ConstantVal) )
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; // do nothing
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@ -308,14 +351,16 @@ void PhyRegAlloc::updateMachineCode()
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Op.setRegForValue( MRI.getReturnAddressReg() );
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}
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else
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if (Val->getValueType() == Value::InstructionVal)
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{
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cout << "!Warning: No LiveRange for: ";
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printValue( Val); cout << " Type: " << Val->getValueType();
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cout << " RegVal=" << Op.getAllocatedRegNum() << endl;
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}
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#endif
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continue;
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}
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@ -376,8 +421,6 @@ void PhyRegAlloc::printMachineCode()
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Op.getOperandType() == MachineOperand::MO_CCRegister ||
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Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) {
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const Value *const Val = Op.getVRegValue () ;
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// ****this code is temporary till NULL Values are fixed
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if( ! Val ) {
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@ -386,8 +429,7 @@ void PhyRegAlloc::printMachineCode()
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}
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// if a label or a constant
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if( (Val->getValueType() == Value::BasicBlockVal) ||
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(Val->getValueType() == Value::ConstantVal) ) {
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if( (Val->getValueType() == Value::BasicBlockVal) ) {
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cout << "\t"; printLabel( Op.getVRegValue () );
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}
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@ -395,7 +437,10 @@ void PhyRegAlloc::printMachineCode()
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// else it must be a register value
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const int RegNum = Op.getAllocatedRegNum();
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//if( RegNum != 1000)
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cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
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// else cout << "\t<*NoReg*>";
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}
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@ -418,6 +463,67 @@ void PhyRegAlloc::printMachineCode()
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}
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//----------------------------------------------------------------------------
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//
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//----------------------------------------------------------------------------
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void PhyRegAlloc::colorCallRetArgs()
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{
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CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
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CallRetInstrListType::const_iterator It = CallRetInstList.begin();
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for( ; It != CallRetInstList.end(); ++It ) {
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const Instruction *const CallRetI = *It;
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unsigned OpCode = (CallRetI)->getOpcode();
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const MachineInstr *CRMI = *((CallRetI->getMachineInstrVec()).begin());
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assert( (TM.getInstrInfo().isReturn(CRMI->getOpCode()) ||
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TM.getInstrInfo().isCall(CRMI->getOpCode()) )
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&& "First Machine Instruction is not a Call/Retrunr" );
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// get the added instructions for this Call/Ret instruciton
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AddedInstrns *AI = AddedInstrMap[ CRMI ];
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if ( !AI ) {
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AI = new AddedInstrns();
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AddedInstrMap[ CRMI ] = AI;
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}
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if( (OpCode == Instruction::Call) )
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MRI.colorCallArgs( (CallInst *) CallRetI, LRI, AI );
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else if (OpCode == Instruction::Ret )
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MRI.colorRetValue( (ReturnInst *) CallRetI, LRI, AI );
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else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
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}
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}
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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void PhyRegAlloc::colorIncomingArgs()
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{
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const BasicBlock *const FirstBB = Meth->front();
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const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
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assert( FirstMI && "No machine instruction in entry BB");
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AddedInstrns *AI = AddedInstrMap[ FirstMI ];
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if ( !AI ) {
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AI = new AddedInstrns();
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AddedInstrMap[ FirstMI ] = AI;
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}
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MRI.colorMethodArgs(Meth, LRI, AI );
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}
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//----------------------------------------------------------------------------
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// Used to generate a label for a basic block
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@ -437,56 +543,56 @@ void PhyRegAlloc::printLabel(const Value *const Val)
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void PhyRegAlloc::allocateRegisters()
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{
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// make sure that we put all register classes into the RegClassList
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// before we call constructLiveRanges (now done in the constructor of
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// PhyRegAlloc class).
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constructLiveRanges(); // create LR info
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if( DEBUG_RA)
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if( DEBUG_RA )
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LRI.printLiveRanges();
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createIGNodeListsAndIGs(); // create IGNode list and IGs
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buildInterferenceGraphs(); // build IGs in all reg classes
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if( DEBUG_RA) {
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if( DEBUG_RA ) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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// print IGs in all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIG();
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}
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LRI.coalesceLRs(); // coalesce all live ranges
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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// print IGs in all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIG();
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}
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// the following three calls must be made in that order since
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// coloring or definitions must come before their uses
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MRI.colorArgs(Meth, LRI); // color method args
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// color call args of call instrns
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MRI.colorCallArgs(CallInstrList, LRI, AddedInstrMap);
|
||||
// color return args
|
||||
MRI.colorRetArg(CallInstrList, LRI, AddedInstrMap);
|
||||
|
||||
|
||||
|
||||
// color all register classes
|
||||
// color all register classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->colorAllRegs();
|
||||
|
||||
|
||||
// color incoming args and call args
|
||||
colorIncomingArgs();
|
||||
colorCallRetArgs();
|
||||
|
||||
|
||||
updateMachineCode();
|
||||
if (DEBUG_RA) {
|
||||
PrintMachineInstructions(Meth);
|
||||
// PrintMachineInstructions(Meth);
|
||||
printMachineCode(); // only for DEBUGGING
|
||||
}
|
||||
}
|
||||
|
||||
@ -4,12 +4,15 @@ LiveRangeInfo::LiveRangeInfo(const Method *const M,
|
||||
const TargetMachine& tm,
|
||||
vector<RegClass *> &RCL)
|
||||
: Meth(M), LiveRangeMap(),
|
||||
TM(tm), RegClassList(RCL)
|
||||
TM(tm), RegClassList(RCL),
|
||||
MRI( tm.getRegInfo()),
|
||||
CallRetInstrList()
|
||||
{ }
|
||||
|
||||
|
||||
// union two live ranges into one. The 2nd LR is deleted. Used for coalescing.
|
||||
// Note: the caller must make sure that L1 and L2 are distinct
|
||||
// Note: the caller must make sure that L1 and L2 are distinct and both
|
||||
// LRs don't have suggested colors
|
||||
|
||||
void LiveRangeInfo::unionAndUpdateLRs(LiveRange *const L1, LiveRange *L2)
|
||||
{
|
||||
@ -24,6 +27,15 @@ void LiveRangeInfo::unionAndUpdateLRs(LiveRange *const L1, LiveRange *L2)
|
||||
L1->add( *L2It ); // add the var in L2 to L1
|
||||
LiveRangeMap[ *L2It ] = L1; // now the elements in L2 should map to L1
|
||||
}
|
||||
|
||||
|
||||
// Now if LROfDef(L1) has a suggested color, it will remain.
|
||||
// But, if LROfUse(L2) has a suggested color, the new range
|
||||
// must have the same color.
|
||||
|
||||
if(L2->hasSuggestedColor())
|
||||
L1->setSuggestedColor( L2->getSuggestedColor() );
|
||||
|
||||
delete ( L2 ); // delete L2 as it is no longer needed
|
||||
}
|
||||
|
||||
@ -58,7 +70,7 @@ void LiveRangeInfo::constructLiveRanges()
|
||||
// create a temp machine op to find the register class of value
|
||||
//const MachineOperand Op(MachineOperand::MO_VirtualRegister);
|
||||
|
||||
unsigned rcid = (TM.getRegInfo()).getRegClassIDOfValue( Val );
|
||||
unsigned rcid = MRI.getRegClassIDOfValue( Val );
|
||||
ArgRange->setRegClass(RegClassList[ rcid ] );
|
||||
|
||||
|
||||
@ -68,16 +80,24 @@ void LiveRangeInfo::constructLiveRanges()
|
||||
}
|
||||
}
|
||||
|
||||
// Now suggest hardware registers for these method args
|
||||
MRI.suggestRegs4MethodArgs(Meth, *this);
|
||||
|
||||
|
||||
|
||||
// Now find speical LLVM instructions (CALL, RET) and LRs in machine
|
||||
// instructions.
|
||||
|
||||
// Now find all LRs for machine the instructions. A new LR will be created
|
||||
// only for defs in the machine instr since, we assume that all Values are
|
||||
// defined before they are used. However, there can be multiple defs for
|
||||
// the same Value in machine instructions.
|
||||
|
||||
Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
|
||||
|
||||
for( ; BBI != Meth->end(); ++BBI) { // go thru BBs in random order
|
||||
|
||||
// Now find all LRs for machine the instructions. A new LR will be created
|
||||
// only for defs in the machine instr since, we assume that all Values are
|
||||
// defined before they are used. However, there can be multiple defs for
|
||||
// the same Value in machine instructions.
|
||||
|
||||
// get the iterator for machine instructions
|
||||
const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
|
||||
MachineCodeForBasicBlock::const_iterator
|
||||
@ -87,12 +107,20 @@ void LiveRangeInfo::constructLiveRanges()
|
||||
for( ; MInstIterator != MIVec.end(); MInstIterator++) {
|
||||
|
||||
const MachineInstr * MInst = *MInstIterator;
|
||||
|
||||
// Now if the machine instruction has special operands that must be
|
||||
// set with a "suggested color", do it here.
|
||||
|
||||
|
||||
if( MRI.handleSpecialMInstr(MInst, *this, RegClassList) )
|
||||
continue;
|
||||
|
||||
|
||||
// iterate over MI operands to find defs
|
||||
for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); OpI++) {
|
||||
for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
|
||||
|
||||
|
||||
// delete later from here ************
|
||||
// delete later from here ************
|
||||
MachineOperand::MachineOperandType OpTyp =
|
||||
OpI.getMachineOperand().getOperandType();
|
||||
|
||||
@ -104,11 +132,21 @@ void LiveRangeInfo::constructLiveRanges()
|
||||
// ************* to here
|
||||
|
||||
|
||||
|
||||
// create a new LR iff this operand is a def
|
||||
if( OpI.isDef() ) {
|
||||
|
||||
const Value *const Def = *OpI;
|
||||
|
||||
|
||||
// Only instruction values are accepted for live ranges here
|
||||
|
||||
if( Def->getValueType() != Value::InstructionVal ) {
|
||||
cout << "\n**%%Error: Def is not an instruction val. Def=";
|
||||
printValue( Def ); cout << endl;
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
LiveRange *DefRange = LiveRangeMap[Def];
|
||||
|
||||
// see LR already there (because of multiple defs)
|
||||
@ -130,7 +168,7 @@ void LiveRangeInfo::constructLiveRanges()
|
||||
OpI.getMachineOperand().getOperandType();
|
||||
|
||||
bool isCC = ( OpTy == MachineOperand::MO_CCRegister);
|
||||
unsigned rcid = (TM.getRegInfo()).getRegClassIDOfValue(
|
||||
unsigned rcid = MRI.getRegClassIDOfValue(
|
||||
OpI.getMachineOperand().getVRegValue(), isCC );
|
||||
|
||||
|
||||
@ -163,6 +201,42 @@ void LiveRangeInfo::constructLiveRanges()
|
||||
|
||||
} // for all machine instructions in the BB
|
||||
|
||||
|
||||
} // for all BBs in method
|
||||
|
||||
// go thru LLVM instructions in the basic block and suggest colors
|
||||
// for their args. Also record all CALL
|
||||
// instructions and Return instructions in the CallRetInstrList
|
||||
// This is done because since there are no reverse pointers in machine
|
||||
// instructions to find the llvm instruction, when we encounter a call
|
||||
// or a return whose args must be specailly colored (e.g., %o's for args)
|
||||
// We have to makes sure that all LRs of call/ret args are added before
|
||||
// doing this. But return value of call will not have a LR.
|
||||
|
||||
BBI = Meth->begin(); // random iterator for BBs
|
||||
|
||||
for( ; BBI != Meth->end(); ++BBI) { // go thru BBs in random order
|
||||
|
||||
BasicBlock::const_iterator InstIt = (*BBI)->begin();
|
||||
|
||||
for( ; InstIt != (*BBI)->end() ; ++InstIt) {
|
||||
|
||||
const Instruction *const CallRetI = *InstIt;
|
||||
unsigned OpCode = (CallRetI)->getOpcode();
|
||||
|
||||
if( (OpCode == Instruction::Call) ) {
|
||||
CallRetInstrList.push_back(CallRetI );
|
||||
MRI.suggestRegs4CallArgs( (CallInst *) CallRetI, *this, RegClassList );
|
||||
}
|
||||
|
||||
else if (OpCode == Instruction::Ret ) {
|
||||
CallRetInstrList.push_back( CallRetI );
|
||||
MRI.suggestReg4RetValue( (ReturnInst *) CallRetI, *this);
|
||||
}
|
||||
|
||||
|
||||
} // for each llvm instr in BB
|
||||
|
||||
} // for all BBs in method
|
||||
|
||||
if( DEBUG_RA)
|
||||
@ -183,7 +257,8 @@ void LiveRangeInfo::coalesceLRs()
|
||||
if the def and op are of the same type
|
||||
if the def and op do not interfere //i.e., not simultaneously live
|
||||
if (degree(LR of def) + degree(LR of op)) <= # avail regs
|
||||
merge2IGNodes(def, op) // i.e., merge 2 LRs
|
||||
if both LRs do not have suggested colors
|
||||
merge2IGNodes(def, op) // i.e., merge 2 LRs
|
||||
|
||||
*/
|
||||
|
||||
@ -253,8 +328,14 @@ void LiveRangeInfo::coalesceLRs()
|
||||
|
||||
if( CombinedDegree <= RCOfDef->getNumOfAvailRegs() ) {
|
||||
|
||||
RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
|
||||
unionAndUpdateLRs(LROfDef, LROfUse);
|
||||
// if both LRs do not have suggested colors
|
||||
if( ! (LROfDef->hasSuggestedColor() &&
|
||||
LROfUse->hasSuggestedColor() ) ) {
|
||||
|
||||
RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
|
||||
unionAndUpdateLRs(LROfDef, LROfUse);
|
||||
}
|
||||
|
||||
|
||||
} // if combined degree is less than # of regs
|
||||
|
||||
@ -289,7 +370,7 @@ void LiveRangeInfo::printLiveRanges()
|
||||
LiveRangeMapType::iterator HMI = LiveRangeMap.begin(); // hash map iterator
|
||||
cout << endl << "Printing Live Ranges from Hash Map:" << endl;
|
||||
for( ; HMI != LiveRangeMap.end() ; HMI ++ ) {
|
||||
if( (*HMI).first ) {
|
||||
if( (*HMI).first && (*HMI).second ) {
|
||||
cout <<" "; printValue((*HMI).first); cout << "\t: ";
|
||||
((*HMI).second)->printSet(); cout << endl;
|
||||
}
|
||||
|
||||
@ -17,8 +17,6 @@ PhyRegAlloc::PhyRegAlloc(const Method *const M,
|
||||
Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
|
||||
MRI( tm.getRegInfo() ),
|
||||
NumOfRegClasses(MRI.getNumOfRegClasses()),
|
||||
CallInstrList(),
|
||||
RetInstrList(),
|
||||
AddedInstrMap()
|
||||
|
||||
{
|
||||
@ -47,10 +45,18 @@ void PhyRegAlloc::createIGNodeListsAndIGs()
|
||||
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
|
||||
|
||||
for( ; HMI != HMIEnd ; ++HMI ) {
|
||||
|
||||
if( (*HMI).first ) {
|
||||
|
||||
LiveRange *L = (*HMI).second; // get the LiveRange
|
||||
LiveRange *L = (*HMI).second; // get the LiveRange
|
||||
|
||||
if( (*HMI).first ) {
|
||||
if( !L) {
|
||||
if( DEBUG_RA) {
|
||||
cout << "\n*?!?Warning: Null liver range found for: ";
|
||||
printValue( (*HMI).first) ; cout << endl;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
// if the Value * is not null, and LR
|
||||
// is not yet written to the IGNodeList
|
||||
if( !(L->getUserIGNode()) ) {
|
||||
@ -155,7 +161,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
|
||||
|
||||
// iterate over all the machine instructions in BB
|
||||
for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
|
||||
|
||||
|
||||
const MachineInstr *const MInst = *MInstIterator;
|
||||
|
||||
// get the LV set after the instruction
|
||||
@ -178,6 +184,8 @@ void PhyRegAlloc::buildInterferenceGraphs()
|
||||
} // for all machine instructions in BB
|
||||
|
||||
|
||||
#if 0
|
||||
|
||||
// go thru LLVM instructions in the basic block and record all CALL
|
||||
// instructions and Return instructions in the CallInstrList
|
||||
// This is done because since there are no reverse pointers in machine
|
||||
@ -194,6 +202,9 @@ void PhyRegAlloc::buildInterferenceGraphs()
|
||||
else if( OpCode == Instruction::Ret )
|
||||
RetInstrList.push_back( *InstIt );
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
} // for all BBs in method
|
||||
|
||||
@ -257,7 +268,38 @@ void PhyRegAlloc::updateMachineCode()
|
||||
// iterate over all the machine instructions in BB
|
||||
for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
|
||||
|
||||
MachineInstr *const MInst = *MInstIterator;
|
||||
MachineInstr *MInst = *MInstIterator;
|
||||
|
||||
|
||||
// If there are instructions before to be added, add them now
|
||||
// ***TODO: Add InstrnsAfter as well
|
||||
if( AddedInstrMap[ MInst ] ) {
|
||||
|
||||
vector<MachineInstr *> &IBef =
|
||||
(AddedInstrMap[MInst])->InstrnsBefore;
|
||||
|
||||
if( ! IBef.empty() ) {
|
||||
|
||||
vector<MachineInstr *>::iterator AdIt;
|
||||
|
||||
for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
|
||||
|
||||
cout << "*ADDED instr opcode: ";
|
||||
cout << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString;
|
||||
cout << endl;
|
||||
|
||||
MInstIterator = MIVec.insert( MInstIterator, *AdIt );
|
||||
++MInstIterator;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
// restart from the topmost instruction added
|
||||
//MInst = *MInstIterator;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
|
||||
|
||||
@ -289,8 +331,9 @@ void PhyRegAlloc::updateMachineCode()
|
||||
cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
|
||||
}
|
||||
|
||||
Op.setRegForValue( -1 ); // mark register as invalid
|
||||
Op.setRegForValue( 1000 ); // mark register as invalid
|
||||
|
||||
#if 0
|
||||
if( ((Val->getType())->isLabelType()) ||
|
||||
(Val->getValueType() == Value::ConstantVal) )
|
||||
; // do nothing
|
||||
@ -308,14 +351,16 @@ void PhyRegAlloc::updateMachineCode()
|
||||
Op.setRegForValue( MRI.getReturnAddressReg() );
|
||||
|
||||
}
|
||||
|
||||
else
|
||||
|
||||
if (Val->getValueType() == Value::InstructionVal)
|
||||
{
|
||||
cout << "!Warning: No LiveRange for: ";
|
||||
printValue( Val); cout << " Type: " << Val->getValueType();
|
||||
cout << " RegVal=" << Op.getAllocatedRegNum() << endl;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -376,8 +421,6 @@ void PhyRegAlloc::printMachineCode()
|
||||
Op.getOperandType() == MachineOperand::MO_CCRegister ||
|
||||
Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) {
|
||||
|
||||
|
||||
|
||||
const Value *const Val = Op.getVRegValue () ;
|
||||
// ****this code is temporary till NULL Values are fixed
|
||||
if( ! Val ) {
|
||||
@ -386,8 +429,7 @@ void PhyRegAlloc::printMachineCode()
|
||||
}
|
||||
|
||||
// if a label or a constant
|
||||
if( (Val->getValueType() == Value::BasicBlockVal) ||
|
||||
(Val->getValueType() == Value::ConstantVal) ) {
|
||||
if( (Val->getValueType() == Value::BasicBlockVal) ) {
|
||||
|
||||
cout << "\t"; printLabel( Op.getVRegValue () );
|
||||
}
|
||||
@ -395,7 +437,10 @@ void PhyRegAlloc::printMachineCode()
|
||||
// else it must be a register value
|
||||
const int RegNum = Op.getAllocatedRegNum();
|
||||
|
||||
//if( RegNum != 1000)
|
||||
|
||||
cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
|
||||
// else cout << "\t<*NoReg*>";
|
||||
|
||||
}
|
||||
|
||||
@ -418,6 +463,67 @@ void PhyRegAlloc::printMachineCode()
|
||||
}
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
void PhyRegAlloc::colorCallRetArgs()
|
||||
{
|
||||
|
||||
CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
|
||||
CallRetInstrListType::const_iterator It = CallRetInstList.begin();
|
||||
|
||||
for( ; It != CallRetInstList.end(); ++It ) {
|
||||
|
||||
const Instruction *const CallRetI = *It;
|
||||
unsigned OpCode = (CallRetI)->getOpcode();
|
||||
|
||||
const MachineInstr *CRMI = *((CallRetI->getMachineInstrVec()).begin());
|
||||
|
||||
|
||||
assert( (TM.getInstrInfo().isReturn(CRMI->getOpCode()) ||
|
||||
TM.getInstrInfo().isCall(CRMI->getOpCode()) )
|
||||
&& "First Machine Instruction is not a Call/Retrunr" );
|
||||
|
||||
// get the added instructions for this Call/Ret instruciton
|
||||
AddedInstrns *AI = AddedInstrMap[ CRMI ];
|
||||
if ( !AI ) {
|
||||
AI = new AddedInstrns();
|
||||
AddedInstrMap[ CRMI ] = AI;
|
||||
}
|
||||
|
||||
if( (OpCode == Instruction::Call) )
|
||||
MRI.colorCallArgs( (CallInst *) CallRetI, LRI, AI );
|
||||
|
||||
|
||||
else if (OpCode == Instruction::Ret )
|
||||
MRI.colorRetValue( (ReturnInst *) CallRetI, LRI, AI );
|
||||
|
||||
|
||||
else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
void PhyRegAlloc::colorIncomingArgs()
|
||||
{
|
||||
const BasicBlock *const FirstBB = Meth->front();
|
||||
const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
|
||||
assert( FirstMI && "No machine instruction in entry BB");
|
||||
|
||||
AddedInstrns *AI = AddedInstrMap[ FirstMI ];
|
||||
if ( !AI ) {
|
||||
AI = new AddedInstrns();
|
||||
AddedInstrMap[ FirstMI ] = AI;
|
||||
}
|
||||
|
||||
MRI.colorMethodArgs(Meth, LRI, AI );
|
||||
}
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Used to generate a label for a basic block
|
||||
@ -437,56 +543,56 @@ void PhyRegAlloc::printLabel(const Value *const Val)
|
||||
|
||||
void PhyRegAlloc::allocateRegisters()
|
||||
{
|
||||
|
||||
// make sure that we put all register classes into the RegClassList
|
||||
// before we call constructLiveRanges (now done in the constructor of
|
||||
// PhyRegAlloc class).
|
||||
|
||||
constructLiveRanges(); // create LR info
|
||||
|
||||
if( DEBUG_RA)
|
||||
if( DEBUG_RA )
|
||||
LRI.printLiveRanges();
|
||||
|
||||
|
||||
createIGNodeListsAndIGs(); // create IGNode list and IGs
|
||||
|
||||
buildInterferenceGraphs(); // build IGs in all reg classes
|
||||
|
||||
|
||||
if( DEBUG_RA) {
|
||||
|
||||
if( DEBUG_RA ) {
|
||||
// print all LRs in all reg classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIGNodeList();
|
||||
|
||||
|
||||
// print IGs in all register classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIG();
|
||||
}
|
||||
|
||||
|
||||
LRI.coalesceLRs(); // coalesce all live ranges
|
||||
|
||||
|
||||
if( DEBUG_RA) {
|
||||
// print all LRs in all reg classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIGNodeList();
|
||||
|
||||
|
||||
// print IGs in all register classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->printIG();
|
||||
}
|
||||
|
||||
|
||||
// the following three calls must be made in that order since
|
||||
// coloring or definitions must come before their uses
|
||||
MRI.colorArgs(Meth, LRI); // color method args
|
||||
// color call args of call instrns
|
||||
MRI.colorCallArgs(CallInstrList, LRI, AddedInstrMap);
|
||||
// color return args
|
||||
MRI.colorRetArg(CallInstrList, LRI, AddedInstrMap);
|
||||
|
||||
|
||||
|
||||
// color all register classes
|
||||
// color all register classes
|
||||
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
||||
RegClassList[ rc ]->colorAllRegs();
|
||||
|
||||
|
||||
// color incoming args and call args
|
||||
colorIncomingArgs();
|
||||
colorCallRetArgs();
|
||||
|
||||
|
||||
updateMachineCode();
|
||||
if (DEBUG_RA) {
|
||||
PrintMachineInstructions(Meth);
|
||||
// PrintMachineInstructions(Meth);
|
||||
printMachineCode(); // only for DEBUGGING
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user