mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
a5ab9648a8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@670 91177308-0d34-0410-b5e6-96231b3b80d8
603 lines
18 KiB
C++
603 lines
18 KiB
C++
#include "llvm/CodeGen/PhyRegAlloc.h"
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cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
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"enable register allocation debugging information",
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clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
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clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
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clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
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//----------------------------------------------------------------------------
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// Constructor: Init local composite objects and create register classes.
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//----------------------------------------------------------------------------
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PhyRegAlloc::PhyRegAlloc(const Method *const M,
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const TargetMachine& tm,
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MethodLiveVarInfo *const Lvi)
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: RegClassList(),
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Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
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MRI( tm.getRegInfo() ),
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NumOfRegClasses(MRI.getNumOfRegClasses()),
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AddedInstrMap()
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{
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// **TODO: use an actual reserved color list
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ReservedColorListType *RCL = new ReservedColorListType();
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// create each RegisterClass and put in RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
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RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
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}
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//----------------------------------------------------------------------------
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// This method initally creates interference graphs (one in each reg class)
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// and IGNodeList (one in each IG). The actual nodes will be pushed later.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::createIGNodeListsAndIGs()
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{
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if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
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// hash map iterator
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LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
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// hash map end
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LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
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for( ; HMI != HMIEnd ; ++HMI ) {
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if( (*HMI).first ) {
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LiveRange *L = (*HMI).second; // get the LiveRange
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if( !L) {
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if( DEBUG_RA) {
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cout << "\n*?!?Warning: Null liver range found for: ";
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printValue( (*HMI).first) ; cout << endl;
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}
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continue;
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}
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// if the Value * is not null, and LR
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// is not yet written to the IGNodeList
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if( !(L->getUserIGNode()) ) {
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RegClass *const RC = // RegClass of first value in the LR
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//RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
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RegClassList[ L->getRegClass()->getID() ];
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RC-> addLRToIG( L ); // add this LR to an IG
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}
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}
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}
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// init RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->createInterferenceGraph();
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if( DEBUG_RA)
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cout << "LRLists Created!" << endl;
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}
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//----------------------------------------------------------------------------
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// This method will add all interferences at for a given instruction.
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// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
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// class as that of live var. The live var passed to this function is the
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// LVset AFTER the instruction
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterference(const Value *const Def,
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const LiveVarSet *const LVSet,
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const bool isCallInst) {
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LiveVarSet::const_iterator LIt = LVSet->begin();
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// get the live range of instruction
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const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
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IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
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assert( IGNodeOfDef );
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RegClass *const RCOfDef = LROfDef->getRegClass();
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// for each live var in live variable set
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for( ; LIt != LVSet->end(); ++LIt) {
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if( DEBUG_RA > 1) {
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cout << "< Def="; printValue(Def);
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cout << ", Lvar="; printValue( *LIt); cout << "> ";
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}
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// get the live range corresponding to live var
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LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
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// LROfVar can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if( LROfVar) {
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if(LROfDef == LROfVar) // do not set interf for same LR
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continue;
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// if 2 reg classes are the same set interference
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if( RCOfDef == LROfVar->getRegClass() ){
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RCOfDef->setInterference( LROfDef, LROfVar);
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}
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//the live range of this var interferes with this call
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if( isCallInst )
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LROfVar->addCallInterference( (const Instruction *const) Def );
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}
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else if(DEBUG_RA > 1) {
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// we will not have LRs for values not explicitly allocated in the
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// instruction stream (e.g., constants)
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cout << " warning: no live range for " ;
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printValue( *LIt); cout << endl; }
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}
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}
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//----------------------------------------------------------------------------
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// This method will walk thru code and create interferences in the IG of
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// each RegClass.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::buildInterferenceGraphs()
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{
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if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator
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MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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const MachineInstr *const MInst = *MInstIterator;
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// get the LV set after the instruction
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const LiveVarSet *const LVSetAI =
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LVI->getLiveVarSetAfterMInst(MInst, *BBI);
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const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
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// iterate over MI operands to find defs
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for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
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if( OpI.isDef() ) {
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// create a new LR iff this operand is a def
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addInterference(*OpI, LVSetAI, isCallInst );
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} //if this is a def
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} // for all operands
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} // for all machine instructions in BB
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#if 0
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// go thru LLVM instructions in the basic block and record all CALL
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// instructions and Return instructions in the CallInstrList
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// This is done because since there are no reverse pointers in machine
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// instructions to find the llvm instruction, when we encounter a call
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// or a return whose args must be specailly colored (e.g., %o's for args)
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BasicBlock::const_iterator InstIt = (*BBI)->begin();
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for( ; InstIt != (*BBI)->end() ; ++ InstIt) {
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unsigned OpCode = (*InstIt)->getOpcode();
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if( OpCode == Instruction::Call )
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CallInstrList.push_back( *InstIt );
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else if( OpCode == Instruction::Ret )
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RetInstrList.push_back( *InstIt );
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}
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#endif
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} // for all BBs in method
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// add interferences for method arguments. Since there are no explict
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// defs in method for args, we have to add them manually
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addInterferencesForArgs(); // add interference for method args
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if( DEBUG_RA)
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cout << "Interference graphs calculted!" << endl;
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}
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//----------------------------------------------------------------------------
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// This method will add interferences for incoming arguments to a method.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterferencesForArgs()
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{
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// get the InSet of root BB
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const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
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// get the argument list
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const Method::ArgumentListType& ArgList = Meth->getArgumentList();
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// get an iterator to arg list
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Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
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for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
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addInterference( *ArgIt, InSet, false ); // add interferences between
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// args and LVars at start
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if( DEBUG_RA > 1) {
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cout << " - %% adding interference for argument ";
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printValue( (const Value *) *ArgIt); cout << endl;
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}
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}
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}
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//----------------------------------------------------------------------------
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// This method is called after register allocation is complete to set the
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// allocated reisters in the machine code. This code will add register numbers
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// to MachineOperands that contain a Value.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::updateMachineCode()
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{
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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// get the iterator for machine instructions
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MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *MInst = *MInstIterator;
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// If there are instructions before to be added, add them now
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// ***TODO: Add InstrnsAfter as well
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if( AddedInstrMap[ MInst ] ) {
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vector<MachineInstr *> &IBef =
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(AddedInstrMap[MInst])->InstrnsBefore;
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if( ! IBef.empty() ) {
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vector<MachineInstr *>::iterator AdIt;
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for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
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cout << "*ADDED instr opcode: ";
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cout << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString;
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cout << endl;
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MInstIterator = MIVec.insert( MInstIterator, *AdIt );
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++MInstIterator;
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}
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}
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// restart from the topmost instruction added
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//MInst = *MInstIterator;
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}
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//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
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for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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Op.getOperandType() == MachineOperand::MO_CCRegister) {
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const Value *const Val = Op.getVRegValue();
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// delete this condition checking later (must assert if Val is null)
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if( !Val) {
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if (DEBUG_RA)
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cout << "Warning: NULL Value found for operand" << endl;
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continue;
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}
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assert( Val && "Value is NULL");
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const LiveRange *const LR = LRI.getLiveRangeForValue(Val);
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if ( !LR ) {
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// nothing to worry if it's a const or a label
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if (DEBUG_RA) {
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cout << "*NO LR for inst opcode: ";
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cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
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}
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Op.setRegForValue( 1000 ); // mark register as invalid
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#if 0
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if( ((Val->getType())->isLabelType()) ||
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(Val->getValueType() == Value::ConstantVal) )
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; // do nothing
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// The return address is not explicitly defined within a
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// method. So, it is not colored by usual algorithm. In that case
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// color it here.
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//else if (TM.getInstrInfo().isCall(MInst->getOpCode()))
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//Op.setRegForValue( MRI.getCallAddressReg() );
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//TM.getInstrInfo().isReturn(MInst->getOpCode())
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else if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ) {
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if (DEBUG_RA) cout << endl << "RETURN found" << endl;
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Op.setRegForValue( MRI.getReturnAddressReg() );
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}
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if (Val->getValueType() == Value::InstructionVal)
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{
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cout << "!Warning: No LiveRange for: ";
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printValue( Val); cout << " Type: " << Val->getValueType();
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cout << " RegVal=" << Op.getAllocatedRegNum() << endl;
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}
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#endif
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continue;
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}
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unsigned RCID = (LR->getRegClass())->getID();
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Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
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int RegNum = MRI.getUnifiedRegNum(RCID, LR->getColor());
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}
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}
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}
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}
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}
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//----------------------------------------------------------------------------
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// This method prints the code with registers after register allocation is
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// complete.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::printMachineCode()
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{
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cout << endl << ";************** Method ";
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cout << Meth->getName() << " *****************" << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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cout << endl ; printLabel( *BBI); cout << ": ";
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// get the iterator for machine instructions
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MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *const MInst = *MInstIterator;
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cout << endl << "\t";
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cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
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//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
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for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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Op.getOperandType() == MachineOperand::MO_CCRegister ||
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Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) {
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const Value *const Val = Op.getVRegValue () ;
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// ****this code is temporary till NULL Values are fixed
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if( ! Val ) {
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cout << "\t<*NULL*>";
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continue;
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}
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// if a label or a constant
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if( (Val->getValueType() == Value::BasicBlockVal) ) {
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cout << "\t"; printLabel( Op.getVRegValue () );
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}
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else {
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// else it must be a register value
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const int RegNum = Op.getAllocatedRegNum();
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//if( RegNum != 1000)
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cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
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// else cout << "\t<*NoReg*>";
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}
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}
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else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
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cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
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}
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else
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cout << "\t" << Op; // use dump field
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}
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}
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cout << endl;
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}
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cout << endl;
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}
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//----------------------------------------------------------------------------
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//
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//----------------------------------------------------------------------------
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void PhyRegAlloc::colorCallRetArgs()
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{
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CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
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CallRetInstrListType::const_iterator It = CallRetInstList.begin();
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for( ; It != CallRetInstList.end(); ++It ) {
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const Instruction *const CallRetI = *It;
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unsigned OpCode = (CallRetI)->getOpcode();
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const MachineInstr *CRMI = *((CallRetI->getMachineInstrVec()).begin());
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assert( (TM.getInstrInfo().isReturn(CRMI->getOpCode()) ||
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TM.getInstrInfo().isCall(CRMI->getOpCode()) )
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&& "First Machine Instruction is not a Call/Retrunr" );
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// get the added instructions for this Call/Ret instruciton
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AddedInstrns *AI = AddedInstrMap[ CRMI ];
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if ( !AI ) {
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AI = new AddedInstrns();
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AddedInstrMap[ CRMI ] = AI;
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}
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if( (OpCode == Instruction::Call) )
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MRI.colorCallArgs( (CallInst *) CallRetI, LRI, AI );
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else if (OpCode == Instruction::Ret )
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MRI.colorRetValue( (ReturnInst *) CallRetI, LRI, AI );
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else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
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}
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}
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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void PhyRegAlloc::colorIncomingArgs()
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{
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const BasicBlock *const FirstBB = Meth->front();
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const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
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assert( FirstMI && "No machine instruction in entry BB");
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AddedInstrns *AI = AddedInstrMap[ FirstMI ];
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if ( !AI ) {
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AI = new AddedInstrns();
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AddedInstrMap[ FirstMI ] = AI;
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}
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MRI.colorMethodArgs(Meth, LRI, AI );
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}
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//----------------------------------------------------------------------------
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// Used to generate a label for a basic block
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//----------------------------------------------------------------------------
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void PhyRegAlloc::printLabel(const Value *const Val)
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{
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if( Val->hasName() )
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cout << Val->getName();
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else
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cout << "Label" << Val;
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}
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//----------------------------------------------------------------------------
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// The entry pont to Register Allocation
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//----------------------------------------------------------------------------
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void PhyRegAlloc::allocateRegisters()
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{
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// make sure that we put all register classes into the RegClassList
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// before we call constructLiveRanges (now done in the constructor of
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// PhyRegAlloc class).
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constructLiveRanges(); // create LR info
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if( DEBUG_RA )
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LRI.printLiveRanges();
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createIGNodeListsAndIGs(); // create IGNode list and IGs
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buildInterferenceGraphs(); // build IGs in all reg classes
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if( DEBUG_RA ) {
|
|
// print all LRs in all reg classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIGNodeList();
|
|
|
|
// print IGs in all register classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIG();
|
|
}
|
|
|
|
LRI.coalesceLRs(); // coalesce all live ranges
|
|
|
|
if( DEBUG_RA) {
|
|
// print all LRs in all reg classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIGNodeList();
|
|
|
|
// print IGs in all register classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->printIG();
|
|
}
|
|
|
|
// color all register classes
|
|
for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[ rc ]->colorAllRegs();
|
|
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|
|
// color incoming args and call args
|
|
colorIncomingArgs();
|
|
colorCallRetArgs();
|
|
|
|
|
|
updateMachineCode();
|
|
if (DEBUG_RA) {
|
|
// PrintMachineInstructions(Meth);
|
|
printMachineCode(); // only for DEBUGGING
|
|
}
|
|
}
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|
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