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https://github.com/c64scene-ar/llvm-6502.git
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[PowerPC] Put PPCEarlyReturn into its own source file
PPCInstrInfo.cpp has ended up containing several small MI-level passes, and this is making the file harder to read than necessary. Split out PPCEarlyReturn into its own source file. NFC. Now that PPCInstrInfo.cpp does not also contain pass implementations, I hope that it will be slightly less unwieldy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227775 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
c4b84657f3
commit
a5c1f106b1
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@ -20,6 +20,7 @@ add_llvm_target(PowerPCCodeGen
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PPCInstrInfo.cpp
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PPCISelDAGToDAG.cpp
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PPCISelLowering.cpp
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PPCEarlyReturn.cpp
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PPCFastISel.cpp
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PPCFrameLowering.cpp
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PPCMCInstLower.cpp
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201
lib/Target/PowerPC/PPCEarlyReturn.cpp
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201
lib/Target/PowerPC/PPCEarlyReturn.cpp
Normal file
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@ -0,0 +1,201 @@
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//===------------- PPCEarlyReturn.cpp - Form Early Returns ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// A pass that form early (predicated) returns. If-conversion handles some of
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// this, but this pass picks up some remaining cases.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCInstrInfo.h"
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#include "MCTargetDesc/PPCPredicates.h"
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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#include "PPCMachineFunctionInfo.h"
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#include "PPCTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-early-ret"
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STATISTIC(NumBCLR, "Number of early conditional returns");
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STATISTIC(NumBLR, "Number of early returns");
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namespace llvm {
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void initializePPCEarlyReturnPass(PassRegistry&);
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}
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namespace {
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// PPCEarlyReturn pass - For simple functions without epilogue code, move
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// returns up, and create conditional returns, to avoid unnecessary
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// branch-to-blr sequences.
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struct PPCEarlyReturn : public MachineFunctionPass {
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static char ID;
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PPCEarlyReturn() : MachineFunctionPass(ID) {
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initializePPCEarlyReturnPass(*PassRegistry::getPassRegistry());
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}
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const TargetInstrInfo *TII;
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protected:
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bool processBlock(MachineBasicBlock &ReturnMBB) {
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bool Changed = false;
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MachineBasicBlock::iterator I = ReturnMBB.begin();
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I = ReturnMBB.SkipPHIsAndLabels(I);
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// The block must be essentially empty except for the blr.
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if (I == ReturnMBB.end() ||
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(I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
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I != ReturnMBB.getLastNonDebugInstr())
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return Changed;
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SmallVector<MachineBasicBlock*, 8> PredToRemove;
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for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(),
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PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) {
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bool OtherReference = false, BlockChanged = false;
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for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) {
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MachineInstrBuilder MIB;
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if (J->getOpcode() == PPC::B) {
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if (J->getOperand(0).getMBB() == &ReturnMBB) {
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// This is an unconditional branch to the return. Replace the
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// branch with a blr.
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MIB =
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BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()));
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MIB.copyImplicitOps(I);
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MachineBasicBlock::iterator K = J--;
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K->eraseFromParent();
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BlockChanged = true;
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++NumBLR;
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continue;
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}
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} else if (J->getOpcode() == PPC::BCC) {
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if (J->getOperand(2).getMBB() == &ReturnMBB) {
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// This is a conditional branch to the return. Replace the branch
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// with a bclr.
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MIB = BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
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.addImm(J->getOperand(0).getImm())
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.addReg(J->getOperand(1).getReg());
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MIB.copyImplicitOps(I);
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MachineBasicBlock::iterator K = J--;
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K->eraseFromParent();
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BlockChanged = true;
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++NumBCLR;
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continue;
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}
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} else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
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if (J->getOperand(1).getMBB() == &ReturnMBB) {
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// This is a conditional branch to the return. Replace the branch
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// with a bclr.
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MIB = BuildMI(**PI, J, J->getDebugLoc(),
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TII->get(J->getOpcode() == PPC::BC ?
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PPC::BCLR : PPC::BCLRn))
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.addReg(J->getOperand(0).getReg());
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MIB.copyImplicitOps(I);
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MachineBasicBlock::iterator K = J--;
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K->eraseFromParent();
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BlockChanged = true;
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++NumBCLR;
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continue;
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}
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} else if (J->isBranch()) {
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if (J->isIndirectBranch()) {
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if (ReturnMBB.hasAddressTaken())
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OtherReference = true;
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} else
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for (unsigned i = 0; i < J->getNumOperands(); ++i)
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if (J->getOperand(i).isMBB() &&
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J->getOperand(i).getMBB() == &ReturnMBB)
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OtherReference = true;
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} else if (!J->isTerminator() && !J->isDebugValue())
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break;
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if (J == (*PI)->begin())
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break;
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--J;
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}
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if ((*PI)->canFallThrough() && (*PI)->isLayoutSuccessor(&ReturnMBB))
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OtherReference = true;
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// Predecessors are stored in a vector and can't be removed here.
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if (!OtherReference && BlockChanged) {
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PredToRemove.push_back(*PI);
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}
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if (BlockChanged)
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Changed = true;
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}
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for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i)
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PredToRemove[i]->removeSuccessor(&ReturnMBB);
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if (Changed && !ReturnMBB.hasAddressTaken()) {
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// We now might be able to merge this blr-only block into its
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// by-layout predecessor.
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if (ReturnMBB.pred_size() == 1 &&
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(*ReturnMBB.pred_begin())->isLayoutSuccessor(&ReturnMBB)) {
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// Move the blr into the preceding block.
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MachineBasicBlock &PrevMBB = **ReturnMBB.pred_begin();
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PrevMBB.splice(PrevMBB.end(), &ReturnMBB, I);
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PrevMBB.removeSuccessor(&ReturnMBB);
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}
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if (ReturnMBB.pred_empty())
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ReturnMBB.eraseFromParent();
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}
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return Changed;
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}
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public:
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bool runOnMachineFunction(MachineFunction &MF) override {
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TII = MF.getSubtarget().getInstrInfo();
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bool Changed = false;
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// If the function does not have at least two blocks, then there is
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// nothing to do.
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if (MF.size() < 2)
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return Changed;
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for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
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MachineBasicBlock &B = *I++;
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if (processBlock(B))
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Changed = true;
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}
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return Changed;
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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}
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INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
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"PowerPC Early-Return Creation", false, false)
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char PPCEarlyReturn::ID = 0;
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FunctionPass*
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llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }
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@ -1605,168 +1605,3 @@ unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
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}
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}
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#undef DEBUG_TYPE
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#define DEBUG_TYPE "ppc-early-ret"
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STATISTIC(NumBCLR, "Number of early conditional returns");
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STATISTIC(NumBLR, "Number of early returns");
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namespace llvm {
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void initializePPCEarlyReturnPass(PassRegistry&);
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}
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namespace {
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// PPCEarlyReturn pass - For simple functions without epilogue code, move
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// returns up, and create conditional returns, to avoid unnecessary
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// branch-to-blr sequences.
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struct PPCEarlyReturn : public MachineFunctionPass {
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static char ID;
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PPCEarlyReturn() : MachineFunctionPass(ID) {
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initializePPCEarlyReturnPass(*PassRegistry::getPassRegistry());
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}
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const TargetInstrInfo *TII;
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protected:
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bool processBlock(MachineBasicBlock &ReturnMBB) {
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bool Changed = false;
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MachineBasicBlock::iterator I = ReturnMBB.begin();
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I = ReturnMBB.SkipPHIsAndLabels(I);
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// The block must be essentially empty except for the blr.
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if (I == ReturnMBB.end() ||
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(I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
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I != ReturnMBB.getLastNonDebugInstr())
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return Changed;
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SmallVector<MachineBasicBlock*, 8> PredToRemove;
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for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(),
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PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) {
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bool OtherReference = false, BlockChanged = false;
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for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) {
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MachineInstrBuilder MIB;
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if (J->getOpcode() == PPC::B) {
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if (J->getOperand(0).getMBB() == &ReturnMBB) {
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// This is an unconditional branch to the return. Replace the
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// branch with a blr.
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MIB =
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BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()));
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MIB.copyImplicitOps(I);
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MachineBasicBlock::iterator K = J--;
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K->eraseFromParent();
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BlockChanged = true;
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++NumBLR;
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continue;
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}
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} else if (J->getOpcode() == PPC::BCC) {
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if (J->getOperand(2).getMBB() == &ReturnMBB) {
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// This is a conditional branch to the return. Replace the branch
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// with a bclr.
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MIB = BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
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.addImm(J->getOperand(0).getImm())
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.addReg(J->getOperand(1).getReg());
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MIB.copyImplicitOps(I);
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MachineBasicBlock::iterator K = J--;
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K->eraseFromParent();
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BlockChanged = true;
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++NumBCLR;
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continue;
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}
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} else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
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if (J->getOperand(1).getMBB() == &ReturnMBB) {
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// This is a conditional branch to the return. Replace the branch
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// with a bclr.
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MIB = BuildMI(**PI, J, J->getDebugLoc(),
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TII->get(J->getOpcode() == PPC::BC ?
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PPC::BCLR : PPC::BCLRn))
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.addReg(J->getOperand(0).getReg());
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MIB.copyImplicitOps(I);
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MachineBasicBlock::iterator K = J--;
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K->eraseFromParent();
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BlockChanged = true;
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++NumBCLR;
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continue;
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}
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} else if (J->isBranch()) {
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if (J->isIndirectBranch()) {
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if (ReturnMBB.hasAddressTaken())
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OtherReference = true;
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} else
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for (unsigned i = 0; i < J->getNumOperands(); ++i)
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if (J->getOperand(i).isMBB() &&
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J->getOperand(i).getMBB() == &ReturnMBB)
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OtherReference = true;
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} else if (!J->isTerminator() && !J->isDebugValue())
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break;
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if (J == (*PI)->begin())
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break;
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--J;
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}
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if ((*PI)->canFallThrough() && (*PI)->isLayoutSuccessor(&ReturnMBB))
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OtherReference = true;
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// Predecessors are stored in a vector and can't be removed here.
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if (!OtherReference && BlockChanged) {
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PredToRemove.push_back(*PI);
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}
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if (BlockChanged)
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Changed = true;
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}
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for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i)
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PredToRemove[i]->removeSuccessor(&ReturnMBB);
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if (Changed && !ReturnMBB.hasAddressTaken()) {
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// We now might be able to merge this blr-only block into its
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// by-layout predecessor.
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if (ReturnMBB.pred_size() == 1 &&
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(*ReturnMBB.pred_begin())->isLayoutSuccessor(&ReturnMBB)) {
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// Move the blr into the preceding block.
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MachineBasicBlock &PrevMBB = **ReturnMBB.pred_begin();
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PrevMBB.splice(PrevMBB.end(), &ReturnMBB, I);
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PrevMBB.removeSuccessor(&ReturnMBB);
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}
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if (ReturnMBB.pred_empty())
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ReturnMBB.eraseFromParent();
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}
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return Changed;
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}
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public:
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bool runOnMachineFunction(MachineFunction &MF) override {
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TII = MF.getSubtarget().getInstrInfo();
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bool Changed = false;
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// If the function does not have at least two blocks, then there is
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// nothing to do.
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if (MF.size() < 2)
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return Changed;
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for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
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MachineBasicBlock &B = *I++;
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if (processBlock(B))
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Changed = true;
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}
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return Changed;
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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}
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INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
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"PowerPC Early-Return Creation", false, false)
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char PPCEarlyReturn::ID = 0;
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FunctionPass*
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llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }
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