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Add instruction encodings / disassembler support for 2rus instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
2013-01-20 17:22:43 +00:00
parent 62b8786d12
commit a68c64fbb2
4 changed files with 113 additions and 23 deletions
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23
test/MC/Disassembler/XCore/xcore.txt
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@@ -234,3 +234,26 @@
# CHECK: sub r4, r2, r5
0x89 0x1a
# 2rus instructions
# CHECK: add r10, r2, 5
0xe9 0x92
# CHECK: eq r2, r1, 0
0x24 0xb0
# CHECK: ldw r5, r6[1]
0x19 0x09
# CHECK: shl r6, r5, 24
0xa6 0xa5
# CHECK: shr r3, r8, 5
0xf1 0xab
# CHECK: stw r3, r2[0]
0x38 0x00
# CHECK: sub r2, r4, 11
0x63 0x9d