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Implement bit propagation through sub nodes, this (re)implements
PowerPC/div-2.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26392 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -598,6 +598,12 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
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}
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}
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break;
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case ISD::SUB:
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// Just use ComputeMaskedBits to compute output bits, there are no
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// simplifications that can be done here, and sub always demands all input
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// bits.
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ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
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break;
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}
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// If we know the value of all of the demanded bits, return this as a
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@ -861,12 +867,32 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
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KnownOne = 0;
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return;
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}
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case ISD::SUB:
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case ISD::SUB: {
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ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0));
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if (!CLHS) return;
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// We know that the top bits of C-X are clear if X contains less bits
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// than C (i.e. no wrap-around can happen). For example, 20-X is
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// positive if we can prove that X is >= 0 and < 16. Remember to update
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// SimplifyDemandedBits if/when this is implemented.
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// positive if we can prove that X is >= 0 and < 16.
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MVT::ValueType VT = CLHS->getValueType(0);
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if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear
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unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
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uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit
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MaskV = ~MaskV & MVT::getIntVTBitMask(VT);
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ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1);
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// If all of the MaskV bits are known to be zero, then we know the output
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// top bits are zero, because we now know that the output is from [0-C].
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if ((KnownZero & MaskV) == MaskV) {
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unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
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KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero.
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KnownOne = 0; // No one bits known.
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} else {
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KnownOne = KnownOne = 0; // Otherwise, nothing known.
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}
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}
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return;
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}
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default:
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// Allow the target to implement this method for its nodes.
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if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
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