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[CodeGenPrepare] Fix the check of the legality of an instruction.
The API expects an ISD opcode, not an IR opcode. Fixes a regression for R600. Related to <rdar://problem/15519855>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201923 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1756,7 +1756,12 @@ AddressingModeMatcher::IsPromotionProfitable(unsigned MatchedSize,
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Instruction *PromotedInst = dyn_cast<Instruction>(PromotedOperand);
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if (!PromotedInst)
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return false;
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return TLI.isOperationLegalOrCustom(PromotedInst->getOpcode(),
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int ISDOpcode = TLI.InstructionOpcodeToISD(PromotedInst->getOpcode());
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// If the ISDOpcode is undefined, it was undefined before the promotion.
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if (!ISDOpcode)
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return true;
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// Otherwise, check if the promoted instruction is legal or not.
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return TLI.isOperationLegalOrCustom(ISDOpcode,
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EVT::getEVT(PromotedInst->getType()));
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}
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@ -1,11 +1,14 @@
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; RUN: opt -codegenprepare -S -o - %s | FileCheck %s
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; RUN: opt -codegenprepare -S -o - %s | FileCheck --check-prefix=OPT --check-prefix=FUNC %s
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; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-LLC --check-prefix=FUNC %s
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target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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target triple = "r600--"
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; CHECK-LABEL: @test
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; CHECK: mul
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; CHECK-NEXT: sext
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; FUNC-LABEL: @test
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; OPT: mul nsw i32
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; OPT-NEXT: sext
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; SI-LLC: V_MUL_LO_I32
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; SI-LLC-NOT: V_MUL_HI
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define void @test(i8 addrspace(1)* nocapture readonly %in, i32 %a, i8 %b) {
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entry:
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%0 = mul nsw i32 %a, 3
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